Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
198 lines
5.3 KiB
C
198 lines
5.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only or MIT */
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/* Copyright 2025 Arm, Ltd. */
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#ifndef __ETHOSU_DEVICE_H__
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#define __ETHOSU_DEVICE_H__
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/types.h>
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#include <drm/drm_device.h>
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#include <drm/gpu_scheduler.h>
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#include <drm/ethosu_accel.h>
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struct clk;
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struct gen_pool;
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#define NPU_REG_ID 0x0000
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#define NPU_REG_STATUS 0x0004
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#define NPU_REG_CMD 0x0008
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#define NPU_REG_RESET 0x000c
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#define NPU_REG_QBASE 0x0010
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#define NPU_REG_QBASE_HI 0x0014
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#define NPU_REG_QREAD 0x0018
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#define NPU_REG_QCONFIG 0x001c
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#define NPU_REG_QSIZE 0x0020
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#define NPU_REG_PROT 0x0024
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#define NPU_REG_CONFIG 0x0028
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#define NPU_REG_REGIONCFG 0x003c
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#define NPU_REG_AXILIMIT0 0x0040 // U65
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#define NPU_REG_AXILIMIT1 0x0044 // U65
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#define NPU_REG_AXILIMIT2 0x0048 // U65
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#define NPU_REG_AXILIMIT3 0x004c // U65
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#define NPU_REG_MEM_ATTR0 0x0040 // U85
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#define NPU_REG_MEM_ATTR1 0x0044 // U85
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#define NPU_REG_MEM_ATTR2 0x0048 // U85
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#define NPU_REG_MEM_ATTR3 0x004c // U85
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#define NPU_REG_AXI_SRAM 0x0050 // U85
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#define NPU_REG_AXI_EXT 0x0054 // U85
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#define NPU_REG_BASEP(x) (0x0080 + (x) * 8)
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#define NPU_REG_BASEP_HI(x) (0x0084 + (x) * 8)
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#define NPU_BASEP_REGION_MAX 8
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#define ID_ARCH_MAJOR_MASK GENMASK(31, 28)
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#define ID_ARCH_MINOR_MASK GENMASK(27, 20)
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#define ID_ARCH_PATCH_MASK GENMASK(19, 16)
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#define ID_VER_MAJOR_MASK GENMASK(11, 8)
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#define ID_VER_MINOR_MASK GENMASK(7, 4)
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#define CONFIG_MACS_PER_CC_MASK GENMASK(3, 0)
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#define CONFIG_CMD_STREAM_VER_MASK GENMASK(7, 4)
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#define STATUS_STATE_RUNNING BIT(0)
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#define STATUS_IRQ_RAISED BIT(1)
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#define STATUS_BUS_STATUS BIT(2)
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#define STATUS_RESET_STATUS BIT(3)
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#define STATUS_CMD_PARSE_ERR BIT(4)
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#define STATUS_CMD_END_REACHED BIT(5)
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#define CMD_CLEAR_IRQ BIT(1)
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#define CMD_TRANSITION_TO_RUN BIT(0)
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#define RESET_PENDING_CSL BIT(1)
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#define RESET_PENDING_CPL BIT(0)
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#define PROT_ACTIVE_CSL BIT(1)
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enum ethosu_cmds {
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NPU_OP_CONV = 0x2,
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NPU_OP_DEPTHWISE = 0x3,
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NPU_OP_POOL = 0x5,
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NPU_OP_ELEMENTWISE = 0x6,
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NPU_OP_RESIZE = 0x7, // U85 only
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NPU_OP_DMA_START = 0x10,
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NPU_SET_IFM_PAD_TOP = 0x100,
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NPU_SET_IFM_PAD_LEFT = 0x101,
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NPU_SET_IFM_PAD_RIGHT = 0x102,
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NPU_SET_IFM_PAD_BOTTOM = 0x103,
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NPU_SET_IFM_DEPTH_M1 = 0x104,
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NPU_SET_IFM_PRECISION = 0x105,
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NPU_SET_IFM_BROADCAST = 0x108,
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NPU_SET_IFM_WIDTH0_M1 = 0x10a,
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NPU_SET_IFM_HEIGHT0_M1 = 0x10b,
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NPU_SET_IFM_HEIGHT1_M1 = 0x10c,
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NPU_SET_IFM_REGION = 0x10f,
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NPU_SET_OFM_WIDTH_M1 = 0x111,
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NPU_SET_OFM_HEIGHT_M1 = 0x112,
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NPU_SET_OFM_DEPTH_M1 = 0x113,
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NPU_SET_OFM_PRECISION = 0x114,
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NPU_SET_OFM_WIDTH0_M1 = 0x11a,
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NPU_SET_OFM_HEIGHT0_M1 = 0x11b,
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NPU_SET_OFM_HEIGHT1_M1 = 0x11c,
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NPU_SET_OFM_REGION = 0x11f,
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NPU_SET_KERNEL_WIDTH_M1 = 0x120,
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NPU_SET_KERNEL_HEIGHT_M1 = 0x121,
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NPU_SET_KERNEL_STRIDE = 0x122,
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NPU_SET_WEIGHT_REGION = 0x128,
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NPU_SET_SCALE_REGION = 0x129,
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NPU_SET_DMA0_SRC_REGION = 0x130,
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NPU_SET_DMA0_DST_REGION = 0x131,
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NPU_SET_DMA0_SIZE0 = 0x132,
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NPU_SET_DMA0_SIZE1 = 0x133,
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NPU_SET_IFM2_BROADCAST = 0x180,
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NPU_SET_IFM2_PRECISION = 0x185,
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NPU_SET_IFM2_WIDTH0_M1 = 0x18a,
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NPU_SET_IFM2_HEIGHT0_M1 = 0x18b,
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NPU_SET_IFM2_HEIGHT1_M1 = 0x18c,
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NPU_SET_IFM2_REGION = 0x18f,
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NPU_SET_IFM_BASE0 = 0x4000,
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NPU_SET_IFM_BASE1 = 0x4001,
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NPU_SET_IFM_BASE2 = 0x4002,
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NPU_SET_IFM_BASE3 = 0x4003,
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NPU_SET_IFM_STRIDE_X = 0x4004,
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NPU_SET_IFM_STRIDE_Y = 0x4005,
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NPU_SET_IFM_STRIDE_C = 0x4006,
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NPU_SET_OFM_BASE0 = 0x4010,
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NPU_SET_OFM_BASE1 = 0x4011,
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NPU_SET_OFM_BASE2 = 0x4012,
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NPU_SET_OFM_BASE3 = 0x4013,
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NPU_SET_OFM_STRIDE_X = 0x4014,
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NPU_SET_OFM_STRIDE_Y = 0x4015,
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NPU_SET_OFM_STRIDE_C = 0x4016,
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NPU_SET_WEIGHT_BASE = 0x4020,
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NPU_SET_WEIGHT_LENGTH = 0x4021,
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NPU_SET_SCALE_BASE = 0x4022,
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NPU_SET_SCALE_LENGTH = 0x4023,
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NPU_SET_DMA0_SRC = 0x4030,
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NPU_SET_DMA0_DST = 0x4031,
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NPU_SET_DMA0_LEN = 0x4032,
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NPU_SET_DMA0_SRC_STRIDE0 = 0x4033,
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NPU_SET_DMA0_SRC_STRIDE1 = 0x4034,
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NPU_SET_DMA0_DST_STRIDE0 = 0x4035,
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NPU_SET_DMA0_DST_STRIDE1 = 0x4036,
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NPU_SET_IFM2_BASE0 = 0x4080,
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NPU_SET_IFM2_BASE1 = 0x4081,
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NPU_SET_IFM2_BASE2 = 0x4082,
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NPU_SET_IFM2_BASE3 = 0x4083,
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NPU_SET_IFM2_STRIDE_X = 0x4084,
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NPU_SET_IFM2_STRIDE_Y = 0x4085,
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NPU_SET_IFM2_STRIDE_C = 0x4086,
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NPU_SET_WEIGHT1_BASE = 0x4090,
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NPU_SET_WEIGHT1_LENGTH = 0x4091,
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NPU_SET_SCALE1_BASE = 0x4092,
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NPU_SET_WEIGHT2_BASE = 0x4092,
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NPU_SET_SCALE1_LENGTH = 0x4093,
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NPU_SET_WEIGHT2_LENGTH = 0x4093,
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NPU_SET_WEIGHT3_BASE = 0x4094,
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NPU_SET_WEIGHT3_LENGTH = 0x4095,
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};
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#define ETHOSU_SRAM_REGION 2 /* Matching Vela compiler */
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/**
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* struct ethosu_device - Ethosu device
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*/
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struct ethosu_device {
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/** @base: Base drm_device. */
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struct drm_device base;
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/** @iomem: CPU mapping of the registers. */
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void __iomem *regs;
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void __iomem *sram;
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struct gen_pool *srampool;
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dma_addr_t sramphys;
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struct clk_bulk_data *clks;
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int num_clks;
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int irq;
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struct drm_ethosu_npu_info npu_info;
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struct ethosu_job *in_flight_job;
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/* For in_flight_job and ethosu_job_hw_submit() */
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struct mutex job_lock;
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/* For dma_fence */
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spinlock_t fence_lock;
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struct drm_gpu_scheduler sched;
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/* For ethosu_job_do_push() */
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struct mutex sched_lock;
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u64 fence_context;
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u64 emit_seqno;
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};
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#define to_ethosu_device(drm_dev) \
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((struct ethosu_device *)container_of(drm_dev, struct ethosu_device, base))
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static inline bool ethosu_is_u65(const struct ethosu_device *ethosudev)
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{
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return FIELD_GET(ID_ARCH_MAJOR_MASK, ethosudev->npu_info.id) == 1;
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}
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#endif
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