Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
44 lines
854 B
C
44 lines
854 B
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2019 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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#ifndef GOYA_H
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#define GOYA_H
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#define SRAM_CFG_BAR_ID 0
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#define MSIX_BAR_ID 2
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#define DDR_BAR_ID 4
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#define CFG_BAR_SIZE 0x10000000ull /* 256MB */
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#define MSIX_BAR_SIZE 0x1000ull /* 4KB */
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#define CFG_BASE 0x7FFC000000ull
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#define CFG_SIZE 0x4000000 /* 32MB CFG + 32MB DBG*/
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#define SRAM_BASE_ADDR 0x7FF0000000ull
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#define SRAM_SIZE 0x32A0000 /* 50.625MB */
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#define DRAM_PHYS_BASE 0x0ull
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#define HOST_PHYS_BASE 0x8000000000ull /* 0.5TB */
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#define HOST_PHYS_SIZE 0x1000000000000ull /* 0.25PB (48 bits) */
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#define GOYA_MSIX_ENTRIES 8
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#define QMAN_PQ_ENTRY_SIZE 16 /* Bytes */
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#define MAX_ASID 2
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#define PROT_BITS_OFFS 0xF80
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#define DMA_MAX_NUM 5
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#define TPC_MAX_NUM 8
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#define MME_MAX_NUM 1
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#endif /* GOYA_H */
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