Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
40 lines
915 B
C
40 lines
915 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* R-Car Gen2 Clock Pulse Generator
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*
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* Copyright (C) 2016 Cogent Embedded Inc.
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*/
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#ifndef __CLK_RENESAS_RCAR_GEN2_CPG_H__
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#define __CLK_RENESAS_RCAR_GEN2_CPG_H__
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enum rcar_gen2_clk_types {
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CLK_TYPE_GEN2_MAIN = CLK_TYPE_CUSTOM,
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CLK_TYPE_GEN2_PLL0,
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CLK_TYPE_GEN2_PLL1,
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CLK_TYPE_GEN2_PLL3,
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CLK_TYPE_GEN2_Z,
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CLK_TYPE_GEN2_LB,
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CLK_TYPE_GEN2_ADSP,
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CLK_TYPE_GEN2_SDH,
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CLK_TYPE_GEN2_SD0,
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CLK_TYPE_GEN2_SD1,
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CLK_TYPE_GEN2_QSPI,
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CLK_TYPE_GEN2_RCAN,
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};
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struct rcar_gen2_cpg_pll_config {
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u8 extal_div;
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u8 pll1_mult;
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u8 pll3_mult;
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u8 pll0_mult; /* leave as zero if PLL0CR exists */
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};
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struct clk *rcar_gen2_cpg_clk_register(struct device *dev,
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const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
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struct cpg_mssr_pub *pub);
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int rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config,
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unsigned int pll0_div, u32 mode);
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#endif
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