Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
35 lines
999 B
C
35 lines
999 B
C
/* SPDX-License-Identifier: GPL-2.0
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* Marvell OcteonTX CPT driver
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*
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* Copyright (C) 2019 Marvell International Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __OTX_CPTPF_H
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#define __OTX_CPTPF_H
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#include <linux/types.h>
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#include <linux/device.h>
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#include "otx_cptpf_ucode.h"
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/*
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* OcteonTX CPT device structure
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*/
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struct otx_cpt_device {
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void __iomem *reg_base; /* Register start address */
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struct pci_dev *pdev; /* Pci device handle */
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struct otx_cpt_eng_grps eng_grps;/* Engine groups information */
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struct list_head list;
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u8 pf_type; /* PF type SE or AE */
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u8 max_vfs; /* Maximum number of VFs supported by the CPT */
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u8 vfs_enabled; /* Number of enabled VFs */
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};
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void otx_cpt_mbox_intr_handler(struct otx_cpt_device *cpt, int mbx);
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void otx_cpt_disable_all_cores(struct otx_cpt_device *cpt);
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#endif /* __OTX_CPTPF_H */
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