Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
51 lines
1.3 KiB
Plaintext
51 lines
1.3 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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config DRM_CDNS_DSI
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tristate "Cadence DPI/DSI bridge"
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select DRM_KMS_HELPER
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select DRM_MIPI_DSI
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select DRM_PANEL_BRIDGE
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select GENERIC_PHY
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select GENERIC_PHY_MIPI_DPHY
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select VIDEOMODE_HELPERS
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depends on OF
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help
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Support Cadence DPI to DSI bridge. This is an internal
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bridge and is meant to be directly embedded in a SoC.
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if DRM_CDNS_DSI
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config DRM_CDNS_DSI_J721E
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bool "J721E Cadence DSI wrapper support"
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default y
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help
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Support J721E Cadence DSI wrapper. The wrapper manages
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the routing of the DSS DPI signal to the Cadence DSI.
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endif
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config DRM_CDNS_MHDP8546
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tristate "Cadence DPI/DP bridge"
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select DRM_DISPLAY_DP_HELPER
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select DRM_DISPLAY_HDCP_HELPER
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select DRM_DISPLAY_HELPER
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select DRM_KMS_HELPER
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select DRM_PANEL_BRIDGE
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depends on OF
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help
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Support Cadence DPI to DP bridge. This is an internal
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bridge and is meant to be directly embedded in a SoC.
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It takes a DPI stream as input and outputs it encoded
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in DP format.
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if DRM_CDNS_MHDP8546
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config DRM_CDNS_MHDP8546_J721E
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depends on ARCH_K3 || COMPILE_TEST
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bool "J721E Cadence DPI/DP wrapper support"
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default y
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help
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Support J721E Cadence DPI/DP wrapper. This is a wrapper
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which adds support for J721E related platform ops. It
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initializes the J721E Display Port and sets up the
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clock and data muxes.
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endif
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