Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
26 lines
715 B
C
26 lines
715 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2024 Intel Corporation
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*/
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#ifndef __INTEL_TDF_H__
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#define __INTEL_TDF_H__
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/*
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* TDF (Transient-Data-Flush) is needed for Xe2+ where special L3:XD caching can
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* be enabled through various PAT index modes. Idea is to use this caching mode
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* when for example rendering onto the display surface, with the promise that
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* KMD will ensure transient cache entries are always flushed by the time we do
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* the display flip, since display engine is never coherent with CPU/GPU caches.
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*/
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struct intel_display;
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#ifdef I915
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static inline void intel_td_flush(struct intel_display *display) {}
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#else
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void intel_td_flush(struct intel_display *display);
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#endif
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#endif
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