Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
38 lines
950 B
C
38 lines
950 B
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
|
/*
|
|
* Copyright (C) 2016 BayLibre, SAS
|
|
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
|
*/
|
|
|
|
/* Video Clock */
|
|
|
|
#ifndef __MESON_VCLK_H
|
|
#define __MESON_VCLK_H
|
|
|
|
#include <drm/drm_modes.h>
|
|
|
|
struct meson_drm;
|
|
|
|
enum {
|
|
MESON_VCLK_TARGET_CVBS = 0,
|
|
MESON_VCLK_TARGET_HDMI = 1,
|
|
MESON_VCLK_TARGET_DMT = 2,
|
|
};
|
|
|
|
/* 27MHz is the CVBS Pixel Clock */
|
|
#define MESON_VCLK_CVBS (27 * 1000 * 1000)
|
|
|
|
enum drm_mode_status
|
|
meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned long long freq);
|
|
enum drm_mode_status
|
|
meson_vclk_vic_supported_freq(struct meson_drm *priv,
|
|
unsigned long long phy_freq,
|
|
unsigned long long vclk_freq);
|
|
|
|
void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
|
|
unsigned long long phy_freq, unsigned long long vclk_freq,
|
|
unsigned long long venc_freq, unsigned long long dac_freq,
|
|
bool hdmi_use_enci);
|
|
|
|
#endif /* __MESON_VCLK_H */
|