Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
74 lines
2.2 KiB
C
74 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
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* Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
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*/
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#ifndef __TIDSS_IRQ_H__
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#define __TIDSS_IRQ_H__
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#include <linux/types.h>
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#include "tidss_drv.h"
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/*
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* The IRQ status from various DISPC IRQ registers are packed into a single
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* value, where the bits are defined as follows:
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*
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* bit group |dev|wb |mrg0|mrg1|mrg2|mrg3|plane0-3| <unused> |
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* bit use |D |fou|FEOL|FEOL|FEOL|FEOL| UUUU | |
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* bit number|0 |1-3|4-7 |8-11| 12-19 | 20-23 | 24-31 |
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*
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* device bits: D = Unused
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* WB bits: f = frame done wb, o = wb buffer overflow,
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* u = wb buffer uncomplete
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* vp bits: F = frame done, E = vsync even, O = vsync odd, L = sync lost
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* plane bits: U = fifo underflow
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*/
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#define DSS_IRQ_DEVICE_FRAMEDONEWB BIT(1)
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#define DSS_IRQ_DEVICE_WBBUFFEROVERFLOW BIT(2)
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#define DSS_IRQ_DEVICE_WBUNCOMPLETEERROR BIT(3)
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#define DSS_IRQ_DEVICE_WB_MASK GENMASK(3, 1)
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#define DSS_IRQ_VP_BIT_N(ch, bit) (4 + 4 * (ch) + (bit))
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#define DSS_IRQ_PLANE_BIT_N(plane, bit) \
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(DSS_IRQ_VP_BIT_N(TIDSS_MAX_PORTS, 0) + 1 * (plane) + (bit))
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#define DSS_IRQ_VP_BIT(ch, bit) BIT(DSS_IRQ_VP_BIT_N((ch), (bit)))
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#define DSS_IRQ_PLANE_BIT(plane, bit) \
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BIT(DSS_IRQ_PLANE_BIT_N((plane), (bit)))
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static inline dispc_irq_t DSS_IRQ_VP_MASK(u32 ch)
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{
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return GENMASK(DSS_IRQ_VP_BIT_N((ch), 3), DSS_IRQ_VP_BIT_N((ch), 0));
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}
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static inline dispc_irq_t DSS_IRQ_PLANE_MASK(u32 plane)
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{
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return GENMASK(DSS_IRQ_PLANE_BIT_N((plane), 0),
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DSS_IRQ_PLANE_BIT_N((plane), 0));
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}
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#define DSS_IRQ_VP_FRAME_DONE(ch) DSS_IRQ_VP_BIT((ch), 0)
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#define DSS_IRQ_VP_VSYNC_EVEN(ch) DSS_IRQ_VP_BIT((ch), 1)
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#define DSS_IRQ_VP_VSYNC_ODD(ch) DSS_IRQ_VP_BIT((ch), 2)
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#define DSS_IRQ_VP_SYNC_LOST(ch) DSS_IRQ_VP_BIT((ch), 3)
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#define DSS_IRQ_PLANE_FIFO_UNDERFLOW(plane) DSS_IRQ_PLANE_BIT((plane), 0)
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struct drm_crtc;
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struct drm_device;
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struct tidss_device;
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void tidss_irq_enable_vblank(struct drm_crtc *crtc);
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void tidss_irq_disable_vblank(struct drm_crtc *crtc);
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int tidss_irq_install(struct drm_device *ddev, unsigned int irq);
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void tidss_irq_uninstall(struct drm_device *ddev);
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void tidss_irq_resume(struct tidss_device *tidss);
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#endif
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