Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
66 lines
1.7 KiB
C
66 lines
1.7 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef _XE_REGS_H_
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#define _XE_REGS_H_
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#include "regs/xe_reg_defs.h"
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#define SOC_BASE 0x280000
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#define GU_CNTL_PROTECTED XE_REG(0x10100C)
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#define DRIVERINT_FLR_DIS REG_BIT(31)
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#define GU_CNTL XE_REG(0x101010)
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#define LMEM_INIT REG_BIT(7)
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#define DRIVERFLR REG_BIT(31)
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#define XEHP_CLOCK_GATE_DIS XE_REG(0x101014)
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#define SGSI_SIDECLK_DIS REG_BIT(17)
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#define GU_DEBUG XE_REG(0x101018)
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#define DRIVERFLR_STATUS REG_BIT(31)
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#define VIRTUAL_CTRL_REG XE_REG(0x10108c)
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#define GUEST_GTT_UPDATE_EN REG_BIT(8)
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#define XEHP_MTCFG_ADDR XE_REG(0x101800)
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#define TILE_COUNT REG_GENMASK(15, 8)
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#define GGC XE_REG(0x108040)
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#define GMS_MASK REG_GENMASK(15, 8)
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#define GGMS_MASK REG_GENMASK(7, 6)
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#define DSMBASE XE_REG(0x1080C0)
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#define BDSM_MASK REG_GENMASK64(63, 20)
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#define GSMBASE XE_REG(0x108100)
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#define STOLEN_RESERVED XE_REG(0x1082c0)
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#define WOPCM_SIZE_MASK REG_GENMASK64(9, 7)
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#define SG_TILE_ADDR_RANGE(_idx) XE_REG(0x1083a0 + (_idx) * 4)
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#define MTL_RP_STATE_CAP XE_REG(0x138000)
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#define MTL_GT_RPA_FREQUENCY XE_REG(0x138008)
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#define MTL_GT_RPE_FREQUENCY XE_REG(0x13800c)
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#define MTL_MEDIAP_STATE_CAP XE_REG(0x138020)
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#define MTL_RPN_CAP_MASK REG_GENMASK(24, 16)
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#define MTL_RP0_CAP_MASK REG_GENMASK(8, 0)
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#define MTL_MPA_FREQUENCY XE_REG(0x138028)
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#define MTL_RPA_MASK REG_GENMASK(8, 0)
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#define MTL_MPE_FREQUENCY XE_REG(0x13802c)
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#define MTL_RPE_MASK REG_GENMASK(8, 0)
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#define VF_CAP_REG XE_REG(0x1901f8, XE_REG_OPTION_VF)
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#define VF_CAP REG_BIT(0)
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#define PVC_RP_STATE_CAP XE_REG(0x281014)
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#endif
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