Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
45 lines
1.1 KiB
C
45 lines
1.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* I3C HCI Quirks
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*
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* Copyright 2024 Advanced Micro Devices, Inc.
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*
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* Authors: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
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* Guruvendra Punugupati <Guruvendra.Punugupati@amd.com>
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*/
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#include <linux/i3c/master.h>
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#include "hci.h"
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/* Timing registers */
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#define HCI_SCL_I3C_OD_TIMING 0x214
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#define HCI_SCL_I3C_PP_TIMING 0x218
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#define HCI_SDA_HOLD_SWITCH_DLY_TIMING 0x230
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/* Timing values to configure 9MHz frequency */
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#define AMD_SCL_I3C_OD_TIMING 0x00cf00cf
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#define AMD_SCL_I3C_PP_TIMING 0x00160016
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#define QUEUE_THLD_CTRL 0xD0
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void amd_set_od_pp_timing(struct i3c_hci *hci)
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{
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u32 data;
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reg_write(HCI_SCL_I3C_OD_TIMING, AMD_SCL_I3C_OD_TIMING);
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reg_write(HCI_SCL_I3C_PP_TIMING, AMD_SCL_I3C_PP_TIMING);
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data = reg_read(HCI_SDA_HOLD_SWITCH_DLY_TIMING);
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/* Configure maximum TX hold time */
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data |= W0_MASK(18, 16);
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reg_write(HCI_SDA_HOLD_SWITCH_DLY_TIMING, data);
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}
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void amd_set_resp_buf_thld(struct i3c_hci *hci)
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{
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u32 data;
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data = reg_read(QUEUE_THLD_CTRL);
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data = data & ~W0_MASK(15, 8);
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reg_write(QUEUE_THLD_CTRL, data);
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}
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