Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
45 lines
1.1 KiB
C
45 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _ARM_SMMU_QCOM_H
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#define _ARM_SMMU_QCOM_H
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struct qcom_smmu {
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struct arm_smmu_device smmu;
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const struct qcom_smmu_match_data *data;
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bool bypass_quirk;
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u8 bypass_cbndx;
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u32 stall_enabled;
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};
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enum qcom_smmu_impl_reg_offset {
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QCOM_SMMU_TBU_PWR_STATUS,
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QCOM_SMMU_STATS_SYNC_INV_TBU_ACK,
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QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR,
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};
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struct qcom_smmu_config {
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const u32 *reg_offset;
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};
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struct qcom_smmu_match_data {
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const struct qcom_smmu_config *cfg;
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const struct arm_smmu_impl *impl;
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const struct arm_smmu_impl *adreno_impl;
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const struct of_device_id * const client_match;
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};
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irqreturn_t qcom_smmu_context_fault(int irq, void *dev);
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#ifdef CONFIG_ARM_SMMU_QCOM_DEBUG
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void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu);
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int qcom_tbu_probe(struct platform_device *pdev);
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#else
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static inline void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu) { }
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static inline int qcom_tbu_probe(struct platform_device *pdev) { return -EINVAL; }
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#endif
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#endif /* _ARM_SMMU_QCOM_H */
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