Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
90 lines
2.5 KiB
C
90 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright © 2022-2024 Rivos Inc.
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* Copyright © 2023 FORTH-ICS/CARV
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*
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* Authors
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* Tomasz Jeznach <tjeznach@rivosinc.com>
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* Nick Kossifidis <mick@ics.forth.gr>
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*/
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#ifndef _RISCV_IOMMU_H_
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#define _RISCV_IOMMU_H_
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#include <linux/iommu.h>
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#include <linux/types.h>
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#include <linux/iopoll.h>
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#include "iommu-bits.h"
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struct riscv_iommu_device;
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struct riscv_iommu_queue {
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atomic_t prod; /* unbounded producer allocation index */
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atomic_t head; /* unbounded shadow ring buffer consumer index */
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atomic_t tail; /* unbounded shadow ring buffer producer index */
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unsigned int mask; /* index mask, queue length - 1 */
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unsigned int irq; /* allocated interrupt number */
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struct riscv_iommu_device *iommu; /* iommu device handling the queue when active */
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void *base; /* ring buffer kernel pointer */
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dma_addr_t phys; /* ring buffer physical address */
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u16 qbr; /* base register offset, head and tail reference */
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u16 qcr; /* control and status register offset */
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u8 qid; /* queue identifier, same as RISCV_IOMMU_INTR_XX */
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};
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struct riscv_iommu_device {
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/* iommu core interface */
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struct iommu_device iommu;
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/* iommu hardware */
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struct device *dev;
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/* hardware control register space */
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void __iomem *reg;
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/* supported and enabled hardware capabilities */
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u64 caps;
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u32 fctl;
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/* available interrupt numbers, MSI or WSI */
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unsigned int irqs[RISCV_IOMMU_INTR_COUNT];
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unsigned int irqs_count;
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unsigned int icvec;
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/* hardware queues */
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struct riscv_iommu_queue cmdq;
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struct riscv_iommu_queue fltq;
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/* device directory */
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unsigned int ddt_mode;
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dma_addr_t ddt_phys;
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u64 *ddt_root;
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};
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int riscv_iommu_init(struct riscv_iommu_device *iommu);
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void riscv_iommu_remove(struct riscv_iommu_device *iommu);
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void riscv_iommu_disable(struct riscv_iommu_device *iommu);
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#define riscv_iommu_readl(iommu, addr) \
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readl_relaxed((iommu)->reg + (addr))
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#define riscv_iommu_readq(iommu, addr) \
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readq_relaxed((iommu)->reg + (addr))
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#define riscv_iommu_writel(iommu, addr, val) \
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writel_relaxed((val), (iommu)->reg + (addr))
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#define riscv_iommu_writeq(iommu, addr, val) \
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writeq_relaxed((val), (iommu)->reg + (addr))
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#define riscv_iommu_readq_timeout(iommu, addr, val, cond, delay_us, timeout_us) \
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readx_poll_timeout(readq_relaxed, (iommu)->reg + (addr), val, cond, \
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delay_us, timeout_us)
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#define riscv_iommu_readl_timeout(iommu, addr, val, cond, delay_us, timeout_us) \
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readx_poll_timeout(readl_relaxed, (iommu)->reg + (addr), val, cond, \
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delay_us, timeout_us)
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#endif
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