Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
154 lines
4.7 KiB
C
154 lines
4.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Rockchip Camera Interface (CIF) Driver
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*
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* Copyright (C) 2018 Rockchip Electronics Co., Ltd.
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* Copyright (C) 2023 Mehdi Djait <mehdi.djait@bootlin.com>
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* Copyright (C) 2025 Michael Riesch <michael.riesch@wolfvision.net>
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*/
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#ifndef _RKCIF_REGS_H
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#define _RKCIF_REGS_H
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#define RKCIF_REGISTER_NOTSUPPORTED 0x420000
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#define RKCIF_FETCH_Y(VAL) ((VAL) & 0x1fff)
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#define RKCIF_XY_COORD(x, y) (((y) << 16) | (x))
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/* DVP register contents */
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#define RKCIF_CTRL_ENABLE_CAPTURE BIT(0)
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#define RKCIF_CTRL_MODE_PINGPONG BIT(1)
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#define RKCIF_CTRL_MODE_LINELOOP BIT(2)
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#define RKCIF_CTRL_AXI_BURST_16 (0xf << 12)
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#define RKCIF_INTEN_FRAME_END_EN BIT(0)
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#define RKCIF_INTEN_LINE_ERR_EN BIT(2)
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#define RKCIF_INTEN_BUS_ERR_EN BIT(6)
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#define RKCIF_INTEN_SCL_ERR_EN BIT(7)
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#define RKCIF_INTEN_PST_INF_FRAME_END_EN BIT(9)
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#define RKCIF_INTSTAT_CLS 0x3ff
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#define RKCIF_INTSTAT_FRAME_END BIT(0)
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#define RKCIF_INTSTAT_LINE_END BIT(1)
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#define RKCIF_INTSTAT_LINE_ERR BIT(2)
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#define RKCIF_INTSTAT_PIX_ERR BIT(3)
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#define RKCIF_INTSTAT_DFIFO_OF BIT(5)
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#define RKCIF_INTSTAT_BUS_ERR BIT(6)
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#define RKCIF_INTSTAT_PRE_INF_FRAME_END BIT(8)
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#define RKCIF_INTSTAT_PST_INF_FRAME_END BIT(9)
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#define RKCIF_INTSTAT_FRAME_END_CLR BIT(0)
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#define RKCIF_INTSTAT_LINE_END_CLR BIT(1)
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#define RKCIF_INTSTAT_LINE_ERR_CLR BIT(2)
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#define RKCIF_INTSTAT_PST_INF_FRAME_END_CLR BIT(9)
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#define RKCIF_INTSTAT_ERR 0xfc
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#define RKCIF_FRAME_STAT_CLS 0x00
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#define RKCIF_FRAME_FRM0_STAT_CLS 0x20
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#define RKCIF_FORMAT_VSY_HIGH_ACTIVE BIT(0)
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#define RKCIF_FORMAT_HSY_LOW_ACTIVE BIT(1)
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#define RKCIF_FORMAT_INPUT_MODE_YUV (0x00 << 2)
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#define RKCIF_FORMAT_INPUT_MODE_PAL (0x02 << 2)
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#define RKCIF_FORMAT_INPUT_MODE_NTSC (0x03 << 2)
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#define RKCIF_FORMAT_INPUT_MODE_BT1120 (0x07 << 2)
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#define RKCIF_FORMAT_INPUT_MODE_RAW (0x04 << 2)
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#define RKCIF_FORMAT_INPUT_MODE_JPEG (0x05 << 2)
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#define RKCIF_FORMAT_INPUT_MODE_MIPI (0x06 << 2)
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#define RKCIF_FORMAT_YUV_INPUT_ORDER_UYVY (0x00 << 5)
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#define RKCIF_FORMAT_YUV_INPUT_ORDER_YVYU (0x01 << 5)
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#define RKCIF_FORMAT_YUV_INPUT_ORDER_VYUY (0x02 << 5)
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#define RKCIF_FORMAT_YUV_INPUT_ORDER_YUYV (0x03 << 5)
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#define RKCIF_FORMAT_YUV_INPUT_422 (0x00 << 7)
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#define RKCIF_FORMAT_YUV_INPUT_420 BIT(7)
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#define RKCIF_FORMAT_INPUT_420_ORDER_ODD BIT(8)
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#define RKCIF_FORMAT_CCIR_INPUT_ORDER_EVEN BIT(9)
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#define RKCIF_FORMAT_RAW_DATA_WIDTH_8 (0x00 << 11)
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#define RKCIF_FORMAT_RAW_DATA_WIDTH_10 (0x01 << 11)
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#define RKCIF_FORMAT_RAW_DATA_WIDTH_12 (0x02 << 11)
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#define RKCIF_FORMAT_YUV_OUTPUT_422 (0x00 << 16)
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#define RKCIF_FORMAT_YUV_OUTPUT_420 BIT(16)
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#define RKCIF_FORMAT_OUTPUT_420_ORDER_EVEN (0x00 << 17)
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#define RKCIF_FORMAT_OUTPUT_420_ORDER_ODD BIT(17)
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#define RKCIF_FORMAT_RAWD_DATA_LITTLE_ENDIAN (0x00 << 18)
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#define RKCIF_FORMAT_RAWD_DATA_BIG_ENDIAN BIT(18)
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#define RKCIF_FORMAT_UV_STORAGE_ORDER_UVUV (0x00 << 19)
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#define RKCIF_FORMAT_UV_STORAGE_ORDER_VUVU BIT(19)
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#define RKCIF_FORMAT_BT1120_CLOCK_SINGLE_EDGES (0x00 << 24)
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#define RKCIF_FORMAT_BT1120_CLOCK_DOUBLE_EDGES BIT(24)
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#define RKCIF_FORMAT_BT1120_TRANSMIT_INTERFACE (0x00 << 25)
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#define RKCIF_FORMAT_BT1120_TRANSMIT_PROGRESS BIT(25)
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#define RKCIF_FORMAT_BT1120_YC_SWAP BIT(26)
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#define RKCIF_SCL_CTRL_ENABLE_SCL_DOWN BIT(0)
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#define RKCIF_SCL_CTRL_ENABLE_SCL_UP BIT(1)
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#define RKCIF_SCL_CTRL_ENABLE_YUV_16BIT_BYPASS BIT(4)
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#define RKCIF_SCL_CTRL_ENABLE_RAW_16BIT_BYPASS BIT(5)
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#define RKCIF_SCL_CTRL_ENABLE_32BIT_BYPASS BIT(6)
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#define RKCIF_SCL_CTRL_DISABLE_32BIT_BYPASS (0x00 << 6)
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#define RKCIF_INTSTAT_F0_READY BIT(0)
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#define RKCIF_INTSTAT_F1_READY BIT(1)
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/* GRF register offsets and contents */
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#define RK3568_GRF_VI_CON0 0x340
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#define RK3568_GRF_VI_CON1 0x344
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#define RK3568_GRF_VI_STATUS0 0x348
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#define RK3568_GRF_VI_CON1_CIF_DATAPATH BIT(9)
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#define RK3568_GRF_VI_CON1_CIF_CLK_DELAYNUM GENMASK(6, 0)
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#define RK3568_GRF_WRITE_ENABLE(x) ((x) << 16)
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enum rkcif_dvp_register_index {
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RKCIF_DVP_CTRL,
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RKCIF_DVP_INTEN,
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RKCIF_DVP_INTSTAT,
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RKCIF_DVP_FOR,
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RKCIF_DVP_LINE_NUM_ADDR,
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RKCIF_DVP_FRM0_ADDR_Y,
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RKCIF_DVP_FRM0_ADDR_UV,
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RKCIF_DVP_FRM1_ADDR_Y,
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RKCIF_DVP_FRM1_ADDR_UV,
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RKCIF_DVP_VIR_LINE_WIDTH,
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RKCIF_DVP_SET_SIZE,
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RKCIF_DVP_SCL_CTRL,
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RKCIF_DVP_CROP,
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RKCIF_DVP_FRAME_STATUS,
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RKCIF_DVP_LAST_LINE,
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RKCIF_DVP_LAST_PIX,
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RKCIF_DVP_REGISTER_MAX
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};
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enum rkcif_mipi_register_index {
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RKCIF_MIPI_CTRL,
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RKCIF_MIPI_INTEN,
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RKCIF_MIPI_INTSTAT,
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RKCIF_MIPI_REGISTER_MAX
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};
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enum rkcif_mipi_id_register_index {
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RKCIF_MIPI_CTRL0,
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RKCIF_MIPI_CTRL1,
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RKCIF_MIPI_FRAME0_ADDR_Y,
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RKCIF_MIPI_FRAME0_ADDR_UV,
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RKCIF_MIPI_FRAME0_VLW_Y,
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RKCIF_MIPI_FRAME0_VLW_UV,
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RKCIF_MIPI_FRAME1_ADDR_Y,
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RKCIF_MIPI_FRAME1_ADDR_UV,
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RKCIF_MIPI_FRAME1_VLW_Y,
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RKCIF_MIPI_FRAME1_VLW_UV,
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RKCIF_MIPI_CROP_START,
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RKCIF_MIPI_ID_REGISTER_MAX
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};
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#endif
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