Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
53 lines
1.5 KiB
C
53 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Register definition file for Samsung MFC V12.x Interface (FIMV) driver
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*
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* Copyright (c) 2020 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*/
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#ifndef _REGS_MFC_V12_H
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#define _REGS_MFC_V12_H
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#include <linux/sizes.h>
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#include "regs-mfc-v10.h"
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/* MFCv12 Context buffer sizes */
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#define MFC_CTX_BUF_SIZE_V12 (30 * SZ_1K)
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#define MFC_H264_DEC_CTX_BUF_SIZE_V12 (2 * SZ_1M)
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#define MFC_OTHER_DEC_CTX_BUF_SIZE_V12 (30 * SZ_1K)
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#define MFC_H264_ENC_CTX_BUF_SIZE_V12 (100 * SZ_1K)
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#define MFC_HEVC_ENC_CTX_BUF_SIZE_V12 (40 * SZ_1K)
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#define MFC_OTHER_ENC_CTX_BUF_SIZE_V12 (25 * SZ_1K)
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/* MFCv12 variant defines */
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#define MAX_FW_SIZE_V12 (SZ_1M)
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#define MAX_CPB_SIZE_V12 (7 * SZ_1M)
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#define MFC_VERSION_V12 0xC0
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#define MFC_NUM_PORTS_V12 1
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#define S5P_FIMV_CODEC_VP9_ENC 27
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#define MFC_CHROMA_PAD_BYTES_V12 256
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#define S5P_FIMV_D_ALIGN_PLANE_SIZE_V12 256
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/* Encoder buffer size for MFCv12 */
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#define ENC_V120_BASE_SIZE(x, y) \
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((((x) + 3) * ((y) + 3) * 8) \
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+ ((((y) * 64) + 2304) * ((x) + 7) / 8))
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#define ENC_V120_H264_ME_SIZE(x, y) \
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ALIGN((ENC_V120_BASE_SIZE(x, y) \
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+ (DIV_ROUND_UP((x) * (y), 64) * 32)), 256)
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#define ENC_V120_MPEG4_ME_SIZE(x, y) \
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ALIGN((ENC_V120_BASE_SIZE(x, y) \
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+ (DIV_ROUND_UP((x) * (y), 128) * 16)), 256)
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#define ENC_V120_VP8_ME_SIZE(x, y) \
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ALIGN(ENC_V120_BASE_SIZE((x), (y)), 256)
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#define ENC_V120_HEVC_ME_SIZE(x, y) \
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ALIGN(((((x) + 3) * ((y) + 3) * 32) \
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+ ((((y) * 128) + 2304) * ((x) + 3) / 4)), 256)
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#endif /*_REGS_MFC_V12_H*/
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