Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
85 lines
2.2 KiB
C
85 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* SDHCI driver for Synopsys DWC_MSHC controller
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*
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* Copyright (C) 2018 Synopsys, Inc. (www.synopsys.com)
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*
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* Authors:
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* Prabu Thangamuthu <prabu.t@synopsys.com>
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* Manjunath M B <manjumb@synopsys.com>
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*/
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#include "sdhci.h"
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#include "sdhci-pci.h"
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#define SDHCI_VENDOR_PTR_R 0xE8
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/* Synopsys vendor specific registers */
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#define SDHC_GPIO_OUT 0x34
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#define SDHC_AT_CTRL_R 0x40
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#define SDHC_SW_TUNE_EN 0x00000010
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/* MMCM DRP */
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#define SDHC_MMCM_DIV_REG 0x1020
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#define DIV_REG_100_MHZ 0x1145
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#define DIV_REG_200_MHZ 0x1083
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#define SDHC_MMCM_CLKFBOUT 0x1024
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#define CLKFBOUT_100_MHZ 0x0000
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#define CLKFBOUT_200_MHZ 0x0080
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#define SDHC_CCLK_MMCM_RST 0x00000001
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static void sdhci_snps_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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u16 clk;
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u32 reg, vendor_ptr;
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vendor_ptr = sdhci_readw(host, SDHCI_VENDOR_PTR_R);
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/* Disable software managed rx tuning */
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reg = sdhci_readl(host, (SDHC_AT_CTRL_R + vendor_ptr));
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reg &= ~SDHC_SW_TUNE_EN;
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sdhci_writel(host, reg, (SDHC_AT_CTRL_R + vendor_ptr));
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if (clock <= 52000000) {
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sdhci_set_clock(host, clock);
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} else {
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/* Assert reset to MMCM */
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reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr));
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reg |= SDHC_CCLK_MMCM_RST;
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sdhci_writel(host, reg, (SDHC_GPIO_OUT + vendor_ptr));
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/* Configure MMCM */
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if (clock == 100000000) {
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sdhci_writel(host, DIV_REG_100_MHZ, SDHC_MMCM_DIV_REG);
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sdhci_writel(host, CLKFBOUT_100_MHZ,
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SDHC_MMCM_CLKFBOUT);
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} else {
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sdhci_writel(host, DIV_REG_200_MHZ, SDHC_MMCM_DIV_REG);
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sdhci_writel(host, CLKFBOUT_200_MHZ,
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SDHC_MMCM_CLKFBOUT);
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}
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/* De-assert reset to MMCM */
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reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr));
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reg &= ~SDHC_CCLK_MMCM_RST;
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sdhci_writel(host, reg, (SDHC_GPIO_OUT + vendor_ptr));
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/* Enable clock */
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clk = SDHCI_PROG_CLOCK_MODE | SDHCI_CLOCK_INT_EN |
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SDHCI_CLOCK_CARD_EN;
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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}
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}
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static const struct sdhci_ops sdhci_snps_ops = {
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.set_clock = sdhci_snps_set_clock,
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.enable_dma = sdhci_pci_enable_dma,
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.set_bus_width = sdhci_set_bus_width,
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.reset = sdhci_reset,
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.set_uhs_signaling = sdhci_set_uhs_signaling,
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};
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const struct sdhci_pci_fixes sdhci_snps = {
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.ops = &sdhci_snps_ops,
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};
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