Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
97 lines
2.3 KiB
C
97 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
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/* kvaser_pciefd common definitions and declarations
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*
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* Copyright (C) 2025 KVASER AB, Sweden. All rights reserved.
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*/
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#ifndef _KVASER_PCIEFD_H
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#define _KVASER_PCIEFD_H
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#include <linux/can/dev.h>
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#include <linux/completion.h>
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#include <linux/pci.h>
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#include <linux/spinlock.h>
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#include <linux/timer.h>
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#include <linux/types.h>
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#include <net/devlink.h>
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#define KVASER_PCIEFD_MAX_CAN_CHANNELS 8UL
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#define KVASER_PCIEFD_DMA_COUNT 2U
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#define KVASER_PCIEFD_DMA_SIZE (4U * 1024U)
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#define KVASER_PCIEFD_CAN_TX_MAX_COUNT 17U
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struct kvaser_pciefd;
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struct kvaser_pciefd_address_offset {
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u32 serdes;
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u32 pci_ien;
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u32 pci_irq;
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u32 sysid;
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u32 loopback;
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u32 kcan_srb_fifo;
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u32 kcan_srb;
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u32 kcan_ch0;
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u32 kcan_ch1;
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};
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struct kvaser_pciefd_irq_mask {
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u32 kcan_rx0;
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u32 kcan_tx[KVASER_PCIEFD_MAX_CAN_CHANNELS];
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u32 all;
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};
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struct kvaser_pciefd_dev_ops {
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void (*kvaser_pciefd_write_dma_map)(struct kvaser_pciefd *pcie,
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dma_addr_t addr, int index);
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};
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struct kvaser_pciefd_driver_data {
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const struct kvaser_pciefd_address_offset *address_offset;
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const struct kvaser_pciefd_irq_mask *irq_mask;
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const struct kvaser_pciefd_dev_ops *ops;
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};
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struct kvaser_pciefd_fw_version {
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u8 major;
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u8 minor;
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u16 build;
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};
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struct kvaser_pciefd_can {
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struct can_priv can;
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struct devlink_port devlink_port;
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struct kvaser_pciefd *kv_pcie;
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void __iomem *reg_base;
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struct can_berr_counter bec;
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u32 ioc;
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u8 cmd_seq;
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u8 tx_max_count;
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u8 tx_idx;
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u8 ack_idx;
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int err_rep_cnt;
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unsigned int completed_tx_pkts;
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unsigned int completed_tx_bytes;
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spinlock_t lock; /* Locks sensitive registers (e.g. MODE) */
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struct timer_list bec_poll_timer;
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struct completion start_comp, flush_comp;
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};
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struct kvaser_pciefd {
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struct pci_dev *pci;
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void __iomem *reg_base;
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struct kvaser_pciefd_can *can[KVASER_PCIEFD_MAX_CAN_CHANNELS];
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const struct kvaser_pciefd_driver_data *driver_data;
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void *dma_data[KVASER_PCIEFD_DMA_COUNT];
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u8 nr_channels;
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u32 bus_freq;
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u32 freq;
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u32 freq_to_ticks_div;
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struct kvaser_pciefd_fw_version fw_version;
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};
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extern const struct devlink_ops kvaser_pciefd_devlink_ops;
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int kvaser_pciefd_devlink_port_register(struct kvaser_pciefd_can *can);
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void kvaser_pciefd_devlink_port_unregister(struct kvaser_pciefd_can *can);
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#endif /* _KVASER_PCIEFD_H */
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