Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
48 lines
1.4 KiB
C
48 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 1999 - 2018 Intel Corporation. */
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#ifndef _E1000E_MANAGE_H_
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#define _E1000E_MANAGE_H_
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bool e1000e_check_mng_mode_generic(struct e1000_hw *hw);
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bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
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s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);
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bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
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enum e1000_mng_mode {
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e1000_mng_mode_none = 0,
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e1000_mng_mode_asf,
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e1000_mng_mode_pt,
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e1000_mng_mode_ipmi,
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e1000_mng_mode_host_if_only
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};
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#define E1000_FACTPS_MNGCG 0x20000000
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#define E1000_FWSM_MODE_MASK 0xE
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#define E1000_FWSM_MODE_SHIFT 1
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#define E1000_MNG_IAMT_MODE 0x3
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#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10
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#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0
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#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
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#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
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#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
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#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
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#define E1000_VFTA_ENTRY_SHIFT 5
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#define E1000_VFTA_ENTRY_MASK 0x7F
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#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
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#define E1000_HICR_EN 0x01 /* Enable bit - RO */
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/* Driver sets this bit when done to put command in RAM */
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#define E1000_HICR_C 0x02
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#define E1000_HICR_SV 0x04 /* Status Validity */
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#define E1000_HICR_FW_RESET_ENABLE 0x40
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#define E1000_HICR_FW_RESET 0x80
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/* Intel(R) Active Management Technology signature */
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#define E1000_IAMT_SIGNATURE 0x544D4149
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#endif
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