Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
32 lines
820 B
C
32 lines
820 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2025, Intel Corporation. */
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#ifndef _ICE_TSPLL_H_
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#define _ICE_TSPLL_H_
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/**
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* struct ice_tspll_params_e82x - E82X TSPLL parameters
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* @refclk_pre_div: Reference clock pre-divisor
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* @post_pll_div: Post PLL divisor
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* @feedback_div: Feedback divisor
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* @frac_n_div: Fractional divisor
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*
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* Clock Generation Unit parameters used to program the PLL based on the
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* selected TIME_REF/TCXO frequency.
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*/
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struct ice_tspll_params_e82x {
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u8 refclk_pre_div;
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u8 post_pll_div;
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u8 feedback_div;
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u32 frac_n_div;
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};
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#define ICE_TSPLL_CK_REFCLKFREQ_E825 0x1F
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#define ICE_TSPLL_NDIVRATIO_E825 5
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#define ICE_TSPLL_FBDIV_INTGR_E825 256
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int ice_tspll_cfg_pps_out_e825c(struct ice_hw *hw, bool enable);
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int ice_tspll_init(struct ice_hw *hw);
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#endif /* _ICE_TSPLL_H_ */
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