Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
27 lines
976 B
C
27 lines
976 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
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#define QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
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/* Only for QMP V5_20 PHY - PCIe PCS registers */
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#define QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2 0x00c
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#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
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#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084
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#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
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#define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0
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#define QPHY_V5_20_PCS_PCIE_PRESET_P10_POST 0x0e0
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#define QPHY_PCIE_V5_20_PCS_G3_RXEQEVAL_TIME 0x0f0
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#define QPHY_PCIE_V5_20_PCS_G4_RXEQEVAL_TIME 0x0f4
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#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc
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#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
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#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c
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#define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184
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#define QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2 0x024
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#define QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2 0x028
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#endif
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