Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
26 lines
1002 B
C
26 lines
1002 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_30_H_
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#define QCOM_PHY_QMP_PCS_PCIE_V6_30_H_
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/* Only for QMP V6_30 PHY - PCIE have different offsets than V6 */
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#define QPHY_PCIE_V6_30_PCS_POWER_STATE_CONFIG2 0x014
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#define QPHY_PCIE_V6_30_PCS_TX_RX_CONFIG 0x020
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#define QPHY_PCIE_V6_30_PCS_ENDPOINT_REFCLK_DRIVE 0x024
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#define QPHY_PCIE_V6_30_PCS_OSC_DTCT_ACTIONS 0x098
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#define QPHY_PCIE_V6_30_PCS_EQ_CONFIG1 0x0a8
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#define QPHY_PCIE_V6_30_PCS_G3_RXEQEVAL_TIME 0x0f8
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#define QPHY_PCIE_V6_30_PCS_G4_RXEQEVAL_TIME 0x0fc
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#define QPHY_PCIE_V6_30_PCS_G4_EQ_CONFIG5 0x110
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#define QPHY_PCIE_V6_30_PCS_G4_PRE_GAIN 0x164
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#define QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG1 0x184
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#define QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG3 0x18c
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#define QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG5 0x194
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#define QPHY_PCIE_V6_30_PCS_G3_FOM_EQ_CONFIG5 0x1b4
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#define QPHY_PCIE_V6_30_PCS_G4_FOM_EQ_CONFIG5 0x1c8
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#endif
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