Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
32 lines
1.2 KiB
C
32 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
/*
|
|
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
|
*/
|
|
|
|
#ifndef QCOM_PHY_QMP_PCS_UFS_V4_H_
|
|
#define QCOM_PHY_QMP_PCS_UFS_V4_H_
|
|
|
|
/* Only for QMP V4 PHY - UFS PCS registers */
|
|
#define QPHY_V4_PCS_UFS_PHY_START 0x000
|
|
#define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004
|
|
#define QPHY_V4_PCS_UFS_SW_RESET 0x008
|
|
#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
|
|
#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
|
|
#define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c
|
|
#define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
|
|
#define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
|
|
#define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
|
|
#define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
|
|
#define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
|
|
#define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
|
|
#define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148
|
|
#define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150
|
|
#define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158
|
|
#define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160
|
|
#define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168
|
|
#define QPHY_V4_PCS_UFS_READY_STATUS 0x180
|
|
#define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8
|
|
#define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0
|
|
|
|
#endif
|