Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
39 lines
1.5 KiB
C
39 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef QCOM_PHY_QMP_PCS_UFS_V6_H_
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#define QCOM_PHY_QMP_PCS_UFS_V6_H_
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/* Only for QMP V6 PHY - UFS PCS registers */
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#define QPHY_V6_PCS_UFS_PHY_START 0x000
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#define QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL 0x004
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#define QPHY_V6_PCS_UFS_SW_RESET 0x008
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#define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
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#define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
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#define QPHY_V6_PCS_UFS_PCS_CTRL1 0x020
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#define QPHY_V6_PCS_UFS_PLL_CNTL 0x02c
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#define QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
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#define QPHY_V6_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
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#define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
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#define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
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#define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
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#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
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#define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
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#define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
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#define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
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#define QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2 0x18c
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#define QPHY_V6_PCS_UFS_TX_PWM_GEAR_BAND 0x178
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#define QPHY_V6_PCS_UFS_TX_HS_GEAR_BAND 0x174
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#define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
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#define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
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#define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
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#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
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#define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4 0x240
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#define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5 0x244
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#define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6 0x248
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#define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7 0x24c
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#endif
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