Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
45 lines
1.7 KiB
C
45 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_PCS_V2_H_
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#define QCOM_PHY_QMP_PCS_V2_H_
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/* Only for QMP V2 PHY - PCS registers */
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#define QPHY_V2_PCS_SW_RESET 0x000
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#define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x004
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#define QPHY_V2_PCS_START_CONTROL 0x008
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#define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x024
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#define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x028
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#define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x054
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#define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x058
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#define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x060
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#define QPHY_V2_PCS_POWER_STATE_CONFIG2 0x064
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#define QPHY_V2_PCS_POWER_STATE_CONFIG4 0x06c
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#define QPHY_V2_PCS_LOCK_DETECT_CONFIG1 0x080
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#define QPHY_V2_PCS_LOCK_DETECT_CONFIG2 0x084
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#define QPHY_V2_PCS_LOCK_DETECT_CONFIG3 0x088
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#define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0
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#define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4
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#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8
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#define QPHY_V2_PCS_FLL_CNTRL1 0x0c0
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#define QPHY_V2_PCS_FLL_CNTRL2 0x0c4
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#define QPHY_V2_PCS_FLL_CNT_VAL_L 0x0c8
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#define QPHY_V2_PCS_FLL_CNT_VAL_H_TOL 0x0cc
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#define QPHY_V2_PCS_FLL_MAN_CODE 0x0d0
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#define QPHY_V2_PCS_AUTONOMOUS_MODE_CTRL 0x0d4
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#define QPHY_V2_PCS_LFPS_RXTERM_IRQ_CLEAR 0x0d8
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#define QPHY_V2_PCS_LFPS_RXTERM_IRQ_STATUS 0x178
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#define QPHY_V2_PCS_USB_PCS_STATUS 0x17c /* USB */
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#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8
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#define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac
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#define QPHY_V2_PCS_SIGDET_CNTRL 0x1b0
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#define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8
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#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
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#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
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#define QPHY_V2_PCS_PCI_PCS_STATUS 0x174 /* PCI */
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#endif
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