Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
20 lines
609 B
C
20 lines
609 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_PCS_V6_30_H_
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#define QCOM_PHY_QMP_PCS_V6_30_H_
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/* Only for QMP V6_30 PHY - PCIe PCS registers */
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#define QPHY_V6_30_PCS_LOCK_DETECT_CONFIG2 0x0cc
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#define QPHY_V6_30_PCS_G3S2_PRE_GAIN 0x17c
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#define QPHY_V6_30_PCS_RX_SIGDET_LVL 0x194
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#define QPHY_V6_30_PCS_ALIGN_DETECT_CONFIG7 0x1dc
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#define QPHY_V6_30_PCS_TX_RX_CONFIG 0x1e0
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#define QPHY_V6_30_PCS_TX_RX_CONFIG2 0x1e4
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#define QPHY_V6_30_PCS_EQ_CONFIG4 0x1fc
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#define QPHY_V6_30_PCS_EQ_CONFIG5 0x200
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#endif
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