Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
31 lines
1.0 KiB
Plaintext
31 lines
1.0 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0
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#
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# Intel x86 Platform-Specific Drivers
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#
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config INTEL_PMC_CORE
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tristate "Intel PMC Core driver"
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depends on PCI
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depends on ACPI
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depends on INTEL_PMT_TELEMETRY
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select INTEL_PMC_SSRAM_TELEMETRY
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help
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The Intel Platform Controller Hub for Intel Core SoCs provides access
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to Power Management Controller registers via various interfaces. This
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driver can utilize debugging capabilities and supported features as
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exposed by the Power Management Controller. It also may perform some
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tasks in the PMC in order to enable transition into the SLPS0 state.
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It should be selected on all Intel platforms supported by the driver.
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Supported features:
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- SLP_S0_RESIDENCY counter
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- PCH IP Power Gating status
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- LTR Ignore / LTR Show
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- MPHY/PLL gating status (Sunrisepoint PCH only)
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- SLPS0 Debug registers (Cannonlake/Icelake PCH)
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- Low Power Mode registers (Tigerlake and beyond)
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- PMC quirks as needed to enable SLPS0/S0ix
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config INTEL_PMC_SSRAM_TELEMETRY
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tristate
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