Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
97 lines
2.6 KiB
C
97 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_MEDIATEK_MT6735_PM_DOMAINS_H
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#define __SOC_MEDIATEK_MT6735_PM_DOMAINS_H
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#include "mtk-pm-domains.h"
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#include <dt-bindings/power/mediatek,mt6735-power-controller.h>
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/*
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* MT6735 power domain support
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*/
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static const struct scpsys_domain_data scpsys_domain_data_mt6735[] = {
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[MT6735_POWER_DOMAIN_MD1] = {
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.name = "md1",
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.sta_mask = PWR_STATUS_MD1,
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.ctl_offs = SPM_MD1_PWR_CON,
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.pwr_sta_offs = SPM_PWR_STATUS,
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.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = 0,
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.bp_cfg = {
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BUS_PROT_INFRA_UPDATE_TOPAXI(MT6735_TOP_AXI_PROT_EN_MD1),
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},
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},
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[MT6735_POWER_DOMAIN_CONN] = {
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.name = "conn",
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.sta_mask = PWR_STATUS_CONN,
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.ctl_offs = SPM_CONN_PWR_CON,
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.pwr_sta_offs = SPM_PWR_STATUS,
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.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = 0,
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.bp_cfg = {
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BUS_PROT_INFRA_UPDATE_TOPAXI(MT6735_TOP_AXI_PROT_EN_CONN),
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},
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},
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[MT6735_POWER_DOMAIN_DIS] = {
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.name = "dis",
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.sta_mask = PWR_STATUS_DISP,
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.ctl_offs = SPM_DIS_PWR_CON,
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.pwr_sta_offs = SPM_PWR_STATUS,
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.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.bp_cfg = {
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BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0),
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},
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},
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[MT6735_POWER_DOMAIN_MFG] = {
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.name = "mfg",
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.sta_mask = PWR_STATUS_MFG,
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.ctl_offs = SPM_MFG_PWR_CON,
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.pwr_sta_offs = SPM_PWR_STATUS,
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.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.bp_cfg = {
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BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S),
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},
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},
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[MT6735_POWER_DOMAIN_ISP] = {
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.name = "isp",
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.sta_mask = PWR_STATUS_ISP,
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.ctl_offs = SPM_ISP_PWR_CON,
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.pwr_sta_offs = SPM_PWR_STATUS,
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.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(13, 12),
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},
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[MT6735_POWER_DOMAIN_VDE] = {
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.name = "vde",
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.sta_mask = PWR_STATUS_VDEC,
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.ctl_offs = SPM_VDE_PWR_CON,
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.pwr_sta_offs = SPM_PWR_STATUS,
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.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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},
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[MT6735_POWER_DOMAIN_VEN] = {
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.name = "ven",
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.sta_mask = BIT(8),
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.ctl_offs = SPM_VEN_PWR_CON,
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.pwr_sta_offs = SPM_PWR_STATUS,
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.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(15, 12),
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},
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};
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static const struct scpsys_soc_data mt6735_scpsys_data = {
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.domains_data = scpsys_domain_data_mt6735,
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.num_domains = ARRAY_SIZE(scpsys_domain_data_mt6735),
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};
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#endif /* __SOC_MEDIATEK_MT6735_PM_DOMAINS_H */
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