Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
76 lines
2.5 KiB
C
76 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Renesas R-Car System Controller
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*
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* Copyright (C) 2016 Glider bvba
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*/
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#ifndef __SOC_RENESAS_RCAR_SYSC_H__
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#define __SOC_RENESAS_RCAR_SYSC_H__
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#include <linux/types.h>
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/*
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* Power Domain flags
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*/
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#define PD_CPU BIT(0) /* Area contains main CPU core */
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#define PD_SCU BIT(1) /* Area contains SCU and L2 cache */
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#define PD_NO_CR BIT(2) /* Area lacks PWR{ON,OFF}CR registers */
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#define PD_OFF_DELAY BIT(3) /* Area is subject to power-off delay quirk */
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#define PD_CPU_CR PD_CPU /* CPU area has CR (R-Car H1) */
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#define PD_CPU_NOCR PD_CPU | PD_NO_CR /* CPU area lacks CR (R-Car Gen2/3) */
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#define PD_ALWAYS_ON PD_NO_CR /* Always-on area */
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/*
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* Description of a Power Area
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*/
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struct rcar_sysc_area {
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const char *name;
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u16 chan_offs; /* Offset of PWRSR register for this area */
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u8 chan_bit; /* Bit in PWR* (except for PWRUP in PWRSR) */
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u8 isr_bit; /* Bit in SYSCI*R */
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s8 parent; /* -1 if none */
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u8 flags; /* See PD_* */
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};
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/*
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* SoC-specific Power Area Description
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*/
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struct rcar_sysc_info {
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int (*init)(void); /* Optional */
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const struct rcar_sysc_area *areas;
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unsigned int num_areas;
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/* Optional External Request Mask Register */
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u32 extmask_offs; /* SYSCEXTMASK register offset */
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u32 extmask_val; /* SYSCEXTMASK register mask value */
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};
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extern const struct rcar_sysc_info r8a7742_sysc_info;
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extern const struct rcar_sysc_info r8a7743_sysc_info;
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extern const struct rcar_sysc_info r8a7745_sysc_info;
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extern const struct rcar_sysc_info r8a77470_sysc_info;
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extern const struct rcar_sysc_info r8a774a1_sysc_info;
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extern const struct rcar_sysc_info r8a774b1_sysc_info;
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extern const struct rcar_sysc_info r8a774c0_sysc_info;
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extern const struct rcar_sysc_info r8a774e1_sysc_info;
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extern const struct rcar_sysc_info r8a7779_sysc_info;
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extern const struct rcar_sysc_info r8a7790_sysc_info;
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extern const struct rcar_sysc_info r8a7791_sysc_info;
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extern const struct rcar_sysc_info r8a7792_sysc_info;
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extern const struct rcar_sysc_info r8a7794_sysc_info;
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extern struct rcar_sysc_info r8a7795_sysc_info;
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extern const struct rcar_sysc_info r8a77960_sysc_info;
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extern const struct rcar_sysc_info r8a77961_sysc_info;
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extern const struct rcar_sysc_info r8a77965_sysc_info;
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extern const struct rcar_sysc_info r8a77970_sysc_info;
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extern const struct rcar_sysc_info r8a77980_sysc_info;
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extern const struct rcar_sysc_info r8a77990_sysc_info;
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extern const struct rcar_sysc_info r8a77995_sysc_info;
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#endif /* __SOC_RENESAS_RCAR_SYSC_H__ */
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