Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
23 lines
585 B
C
23 lines
585 B
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H
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#define _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H
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/* CMN PLL core clock. */
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#define CMN_PLL_CLK 0
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/* The output clocks from CMN PLL of IPQ9574. */
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#define XO_24MHZ_CLK 1
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#define SLEEP_32KHZ_CLK 2
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#define PCS_31P25MHZ_CLK 3
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#define NSS_1200MHZ_CLK 4
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#define PPE_353MHZ_CLK 5
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#define ETH0_50MHZ_CLK 6
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#define ETH1_50MHZ_CLK 7
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#define ETH2_50MHZ_CLK 8
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#define ETH_25MHZ_CLK 9
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#endif
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