Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
29 lines
957 B
C
29 lines
957 B
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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*
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* Copyright (C) 2024 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__
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#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* Core Clock list */
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#define R9A09G047_SYS_0_PCLK 0
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#define R9A09G047_CA55_0_CORECLK0 1
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#define R9A09G047_CA55_0_CORECLK1 2
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#define R9A09G047_CA55_0_CORECLK2 3
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#define R9A09G047_CA55_0_CORECLK3 4
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#define R9A09G047_CA55_0_PERIPHCLK 5
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#define R9A09G047_CM33_CLK0 6
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#define R9A09G047_CST_0_SWCLKTCK 7
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#define R9A09G047_IOTOP_0_SHCLK 8
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#define R9A09G047_SPI_CLK_SPI 9
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#define R9A09G047_GBETH_0_CLK_PTP_REF_I 10
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#define R9A09G047_GBETH_1_CLK_PTP_REF_I 11
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#define R9A09G047_USB3_0_REF_ALT_CLK_P 12
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#define R9A09G047_USB3_0_CLKCORE 13
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#define R9A09G047_USB2_0_CLK_CORE0 14
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#define R9A09G047_USB2_0_CLK_CORE1 15
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#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */
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