Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
56 lines
1.7 KiB
C
56 lines
1.7 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Sam Shih <sam.shih@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7986
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#define _DT_BINDINGS_RESET_CONTROLLER_MT7986
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/* INFRACFG resets */
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#define MT7986_INFRACFG_PEXTP_MAC_SW_RST 6
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#define MT7986_INFRACFG_SSUSB_SW_RST 7
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#define MT7986_INFRACFG_EIP97_SW_RST 8
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#define MT7986_INFRACFG_AUDIO_SW_RST 13
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#define MT7986_INFRACFG_CQ_DMA_SW_RST 14
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#define MT7986_INFRACFG_TRNG_SW_RST 17
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#define MT7986_INFRACFG_AP_DMA_SW_RST 32
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#define MT7986_INFRACFG_I2C_SW_RST 33
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#define MT7986_INFRACFG_NFI_SW_RST 34
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#define MT7986_INFRACFG_SPI0_SW_RST 35
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#define MT7986_INFRACFG_SPI1_SW_RST 36
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#define MT7986_INFRACFG_UART0_SW_RST 37
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#define MT7986_INFRACFG_UART1_SW_RST 38
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#define MT7986_INFRACFG_UART2_SW_RST 39
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#define MT7986_INFRACFG_AUXADC_SW_RST 43
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#define MT7986_INFRACFG_APXGPT_SW_RST 66
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#define MT7986_INFRACFG_PWM_SW_RST 68
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#define MT7986_INFRACFG_SW_RST_NUM 69
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/* TOPRGU resets */
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#define MT7986_TOPRGU_APMIXEDSYS_SW_RST 0
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#define MT7986_TOPRGU_SGMII0_SW_RST 1
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#define MT7986_TOPRGU_SGMII1_SW_RST 2
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#define MT7986_TOPRGU_INFRA_SW_RST 3
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#define MT7986_TOPRGU_U2PHY_SW_RST 5
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#define MT7986_TOPRGU_PCIE_SW_RST 6
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#define MT7986_TOPRGU_SSUSB_SW_RST 7
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#define MT7986_TOPRGU_ETHDMA_SW_RST 20
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#define MT7986_TOPRGU_CONSYS_SW_RST 23
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#define MT7986_TOPRGU_SW_RST_NUM 24
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/* ETHSYS Subsystem resets */
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#define MT7986_ETHSYS_FE_SW_RST 6
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#define MT7986_ETHSYS_PMTR_SW_RST 8
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#define MT7986_ETHSYS_GMAC_SW_RST 23
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#define MT7986_ETHSYS_PPE0_SW_RST 30
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#define MT7986_ETHSYS_PPE1_SW_RST 31
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#define MT7986_ETHSYS_SW_RST_NUM 32
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#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7986 */
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