Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
92 lines
2.7 KiB
C
92 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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// Copyright (c) 2019 Nuvoton Technology corporation.
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#ifndef _DT_BINDINGS_NPCM7XX_RESET_H
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#define _DT_BINDINGS_NPCM7XX_RESET_H
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#define NPCM7XX_RESET_IPSRST1 0x20
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#define NPCM7XX_RESET_IPSRST2 0x24
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#define NPCM7XX_RESET_IPSRST3 0x34
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/* Reset lines on IP1 reset module (NPCM7XX_RESET_IPSRST1) */
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#define NPCM7XX_RESET_FIU3 1
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#define NPCM7XX_RESET_UDC1 5
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#define NPCM7XX_RESET_EMC1 6
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#define NPCM7XX_RESET_UART_2_3 7
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#define NPCM7XX_RESET_UDC2 8
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#define NPCM7XX_RESET_PECI 9
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#define NPCM7XX_RESET_AES 10
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#define NPCM7XX_RESET_UART_0_1 11
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#define NPCM7XX_RESET_MC 12
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#define NPCM7XX_RESET_SMB2 13
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#define NPCM7XX_RESET_SMB3 14
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#define NPCM7XX_RESET_SMB4 15
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#define NPCM7XX_RESET_SMB5 16
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#define NPCM7XX_RESET_PWM_M0 18
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#define NPCM7XX_RESET_TIMER_0_4 19
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#define NPCM7XX_RESET_TIMER_5_9 20
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#define NPCM7XX_RESET_EMC2 21
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#define NPCM7XX_RESET_UDC4 22
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#define NPCM7XX_RESET_UDC5 23
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#define NPCM7XX_RESET_UDC6 24
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#define NPCM7XX_RESET_UDC3 25
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#define NPCM7XX_RESET_ADC 27
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#define NPCM7XX_RESET_SMB6 28
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#define NPCM7XX_RESET_SMB7 29
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#define NPCM7XX_RESET_SMB0 30
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#define NPCM7XX_RESET_SMB1 31
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/* Reset lines on IP2 reset module (NPCM7XX_RESET_IPSRST2) */
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#define NPCM7XX_RESET_MFT0 0
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#define NPCM7XX_RESET_MFT1 1
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#define NPCM7XX_RESET_MFT2 2
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#define NPCM7XX_RESET_MFT3 3
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#define NPCM7XX_RESET_MFT4 4
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#define NPCM7XX_RESET_MFT5 5
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#define NPCM7XX_RESET_MFT6 6
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#define NPCM7XX_RESET_MFT7 7
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#define NPCM7XX_RESET_MMC 8
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#define NPCM7XX_RESET_SDHC 9
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#define NPCM7XX_RESET_GFX_SYS 10
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#define NPCM7XX_RESET_AHB_PCIBRG 11
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#define NPCM7XX_RESET_VDMA 12
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#define NPCM7XX_RESET_ECE 13
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#define NPCM7XX_RESET_VCD 14
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#define NPCM7XX_RESET_OTP 16
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#define NPCM7XX_RESET_SIOX1 18
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#define NPCM7XX_RESET_SIOX2 19
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#define NPCM7XX_RESET_3DES 21
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#define NPCM7XX_RESET_PSPI1 22
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#define NPCM7XX_RESET_PSPI2 23
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#define NPCM7XX_RESET_GMAC2 25
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#define NPCM7XX_RESET_USB_HOST 26
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#define NPCM7XX_RESET_GMAC1 28
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#define NPCM7XX_RESET_CP 31
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/* Reset lines on IP3 reset module (NPCM7XX_RESET_IPSRST3) */
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#define NPCM7XX_RESET_PWM_M1 0
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#define NPCM7XX_RESET_SMB12 1
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#define NPCM7XX_RESET_SPIX 2
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#define NPCM7XX_RESET_SMB13 3
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#define NPCM7XX_RESET_UDC0 4
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#define NPCM7XX_RESET_UDC7 5
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#define NPCM7XX_RESET_UDC8 6
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#define NPCM7XX_RESET_UDC9 7
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#define NPCM7XX_RESET_PCI_MAILBOX 9
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#define NPCM7XX_RESET_SMB14 12
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#define NPCM7XX_RESET_SHA 13
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#define NPCM7XX_RESET_SEC_ECC 14
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#define NPCM7XX_RESET_PCIE_RC 15
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#define NPCM7XX_RESET_TIMER_10_14 16
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#define NPCM7XX_RESET_RNG 17
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#define NPCM7XX_RESET_SMB15 18
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#define NPCM7XX_RESET_SMB8 19
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#define NPCM7XX_RESET_SMB9 20
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#define NPCM7XX_RESET_SMB10 21
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#define NPCM7XX_RESET_SMB11 22
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#define NPCM7XX_RESET_ESPI 23
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#define NPCM7XX_RESET_USB_PHY_1 24
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#define NPCM7XX_RESET_USB_PHY_2 25
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#endif
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