Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
212 lines
4.9 KiB
C
212 lines
4.9 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2023-2025 Rockchip Electronics Co., Ltd.
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* Author: Finley Xiao <finley.xiao@rock-chips.com>
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*/
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#ifndef _DT_BINDINGS_REST_ROCKCHIP_RK3506_H
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#define _DT_BINDINGS_REST_ROCKCHIP_RK3506_H
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/* CRU-->SOFTRST_CON00 */
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#define SRST_NCOREPORESET0_AC 0
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#define SRST_NCOREPORESET1_AC 1
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#define SRST_NCOREPORESET2_AC 2
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#define SRST_NCORESET0_AC 3
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#define SRST_NCORESET1_AC 4
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#define SRST_NCORESET2_AC 5
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#define SRST_NL2RESET_AC 6
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#define SRST_A_CORE_BIU_AC 7
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#define SRST_H_M0_AC 8
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/* CRU-->SOFTRST_CON02 */
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#define SRST_NDBGRESET 9
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#define SRST_P_CORE_BIU 10
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#define SRST_PMU 11
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/* CRU-->SOFTRST_CON03 */
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#define SRST_P_DBG 12
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#define SRST_POT_DBG 13
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#define SRST_P_CORE_GRF 14
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#define SRST_CORE_EMA_DETECT 15
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#define SRST_REF_PVTPLL_CORE 16
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#define SRST_P_GPIO1 17
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#define SRST_DB_GPIO1 18
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/* CRU-->SOFTRST_CON04 */
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#define SRST_A_CORE_PERI_BIU 19
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#define SRST_A_DSMC 20
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#define SRST_P_DSMC 21
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#define SRST_FLEXBUS 22
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#define SRST_A_FLEXBUS 23
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#define SRST_H_FLEXBUS 24
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#define SRST_A_DSMC_SLV 25
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#define SRST_H_DSMC_SLV 26
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#define SRST_DSMC_SLV 27
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/* CRU-->SOFTRST_CON05 */
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#define SRST_A_BUS_BIU 28
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#define SRST_H_BUS_BIU 29
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#define SRST_P_BUS_BIU 30
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#define SRST_A_SYSRAM 31
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#define SRST_H_SYSRAM 32
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#define SRST_A_DMAC0 33
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#define SRST_A_DMAC1 34
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#define SRST_H_M0 35
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#define SRST_M0_JTAG 36
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#define SRST_H_CRYPTO 37
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/* CRU-->SOFTRST_CON06 */
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#define SRST_H_RNG 38
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#define SRST_P_BUS_GRF 39
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#define SRST_P_TIMER0 40
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#define SRST_TIMER0_CH0 41
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#define SRST_TIMER0_CH1 42
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#define SRST_TIMER0_CH2 43
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#define SRST_TIMER0_CH3 44
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#define SRST_TIMER0_CH4 45
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#define SRST_TIMER0_CH5 46
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#define SRST_P_WDT0 47
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#define SRST_T_WDT0 48
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#define SRST_P_WDT1 49
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#define SRST_T_WDT1 50
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#define SRST_P_MAILBOX 51
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#define SRST_P_INTMUX 52
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#define SRST_P_SPINLOCK 53
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/* CRU-->SOFTRST_CON07 */
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#define SRST_P_DDRC 54
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#define SRST_H_DDRPHY 55
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#define SRST_P_DDRMON 56
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#define SRST_DDRMON_OSC 57
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#define SRST_P_DDR_LPC 58
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#define SRST_H_USBOTG0 59
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#define SRST_USBOTG0_ADP 60
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#define SRST_H_USBOTG1 61
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#define SRST_USBOTG1_ADP 62
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#define SRST_P_USBPHY 63
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#define SRST_USBPHY_POR 64
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#define SRST_USBPHY_OTG0 65
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#define SRST_USBPHY_OTG1 66
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/* CRU-->SOFTRST_CON08 */
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#define SRST_A_DMA2DDR 67
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#define SRST_P_DMA2DDR 68
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/* CRU-->SOFTRST_CON09 */
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#define SRST_USBOTG0_UTMI 69
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#define SRST_USBOTG1_UTMI 70
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/* CRU-->SOFTRST_CON10 */
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#define SRST_A_DDRC_0 71
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#define SRST_A_DDRC_1 72
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#define SRST_A_DDR_BIU 73
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#define SRST_DDRC 74
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#define SRST_DDRMON 75
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/* CRU-->SOFTRST_CON11 */
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#define SRST_H_LSPERI_BIU 76
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#define SRST_P_UART0 77
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#define SRST_P_UART1 78
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#define SRST_P_UART2 79
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#define SRST_P_UART3 80
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#define SRST_P_UART4 81
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#define SRST_UART0 82
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#define SRST_UART1 83
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#define SRST_UART2 84
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#define SRST_UART3 85
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#define SRST_UART4 86
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#define SRST_P_I2C0 87
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#define SRST_I2C0 88
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/* CRU-->SOFTRST_CON12 */
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#define SRST_P_I2C1 89
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#define SRST_I2C1 90
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#define SRST_P_I2C2 91
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#define SRST_I2C2 92
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#define SRST_P_PWM1 93
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#define SRST_PWM1 94
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#define SRST_P_SPI0 95
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#define SRST_SPI0 96
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#define SRST_P_SPI1 97
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#define SRST_SPI1 98
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#define SRST_P_GPIO2 99
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#define SRST_DB_GPIO2 100
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/* CRU-->SOFTRST_CON13 */
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#define SRST_P_GPIO3 101
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#define SRST_DB_GPIO3 102
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#define SRST_P_GPIO4 103
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#define SRST_DB_GPIO4 104
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#define SRST_H_CAN0 105
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#define SRST_CAN0 106
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#define SRST_H_CAN1 107
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#define SRST_CAN1 108
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#define SRST_H_PDM 109
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#define SRST_M_PDM 110
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#define SRST_PDM 111
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#define SRST_SPDIFTX 112
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#define SRST_H_SPDIFTX 113
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#define SRST_H_SPDIFRX 114
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#define SRST_SPDIFRX 115
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#define SRST_M_SAI0 116
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/* CRU-->SOFTRST_CON14 */
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#define SRST_H_SAI0 117
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#define SRST_M_SAI1 118
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#define SRST_H_SAI1 119
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#define SRST_H_ASRC0 120
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#define SRST_ASRC0 121
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#define SRST_H_ASRC1 122
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#define SRST_ASRC1 123
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/* CRU-->SOFTRST_CON17 */
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#define SRST_H_HSPERI_BIU 124
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#define SRST_H_SDMMC 125
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#define SRST_H_FSPI 126
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#define SRST_S_FSPI 127
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#define SRST_P_SPI2 128
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#define SRST_A_MAC0 129
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#define SRST_A_MAC1 130
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/* CRU-->SOFTRST_CON18 */
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#define SRST_M_SAI2 131
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#define SRST_H_SAI2 132
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#define SRST_H_SAI3 133
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#define SRST_M_SAI3 134
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#define SRST_H_SAI4 135
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#define SRST_M_SAI4 136
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#define SRST_H_DSM 137
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#define SRST_M_DSM 138
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#define SRST_P_AUDIO_ADC 139
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#define SRST_M_AUDIO_ADC 140
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/* CRU-->SOFTRST_CON19 */
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#define SRST_P_SARADC 141
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#define SRST_SARADC 142
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#define SRST_SARADC_PHY 143
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#define SRST_P_OTPC_NS 144
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#define SRST_SBPI_OTPC_NS 145
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#define SRST_USER_OTPC_NS 146
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#define SRST_P_UART5 147
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#define SRST_UART5 148
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#define SRST_P_GPIO234_IOC 149
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/* CRU-->SOFTRST_CON21 */
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#define SRST_A_VIO_BIU 150
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#define SRST_H_VIO_BIU 151
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#define SRST_H_RGA 152
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#define SRST_A_RGA 153
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#define SRST_CORE_RGA 154
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#define SRST_A_VOP 155
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#define SRST_H_VOP 156
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#define SRST_VOP 157
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#define SRST_P_DPHY 158
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#define SRST_P_DSI_HOST 159
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#define SRST_P_TSADC 160
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#define SRST_TSADC 161
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/* CRU-->SOFTRST_CON22 */
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#define SRST_P_GPIO1_IOC 162
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#endif
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