Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
31 lines
906 B
C
31 lines
906 B
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Definitions for CS4271 ASoC codec driver
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*
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* Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru>
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*/
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#ifndef __CS4271_H
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#define __CS4271_H
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struct cs4271_platform_data {
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bool amutec_eq_bmutec; /* flag to enable AMUTEC=BMUTEC */
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/*
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* The CS4271 requires its LRCLK and MCLK to be stable before its RESET
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* line is de-asserted. That also means that clocks cannot be changed
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* without putting the chip back into hardware reset, which also requires
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* a complete re-initialization of all registers.
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*
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* One (undocumented) workaround is to assert and de-assert the PDN bit
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* in the MODE2 register. This workaround can be enabled with the
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* following flag.
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*
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* Note that this is not needed in case the clocks are stable
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* throughout the entire runtime of the codec.
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*/
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bool enable_soft_reset;
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};
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#endif /* __CS4271_H */
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