Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
75 lines
2.0 KiB
C
75 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef WM8766_H_INCLUDED
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#define WM8766_H_INCLUDED
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#define WM8766_LDA1 0x00
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#define WM8766_RDA1 0x01
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#define WM8766_DAC_CTRL 0x02
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#define WM8766_INT_CTRL 0x03
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#define WM8766_LDA2 0x04
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#define WM8766_RDA2 0x05
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#define WM8766_LDA3 0x06
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#define WM8766_RDA3 0x07
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#define WM8766_MASTDA 0x08
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#define WM8766_DAC_CTRL2 0x09
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#define WM8766_DAC_CTRL3 0x0a
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#define WM8766_MUTE1 0x0c
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#define WM8766_MUTE2 0x0f
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#define WM8766_RESET 0x1f
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/* LDAx/RDAx/MASTDA */
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#define WM8766_ATT_MASK 0x0ff
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#define WM8766_UPDATE 0x100
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/* DAC_CTRL */
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#define WM8766_MUTEALL 0x001
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#define WM8766_DEEMPALL 0x002
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#define WM8766_PWDN 0x004
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#define WM8766_ATC 0x008
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#define WM8766_IZD 0x010
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#define WM8766_PL_LEFT_MASK 0x060
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#define WM8766_PL_LEFT_MUTE 0x000
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#define WM8766_PL_LEFT_LEFT 0x020
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#define WM8766_PL_LEFT_RIGHT 0x040
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#define WM8766_PL_LEFT_LRMIX 0x060
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#define WM8766_PL_RIGHT_MASK 0x180
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#define WM8766_PL_RIGHT_MUTE 0x000
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#define WM8766_PL_RIGHT_LEFT 0x080
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#define WM8766_PL_RIGHT_RIGHT 0x100
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#define WM8766_PL_RIGHT_LRMIX 0x180
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/* INT_CTRL */
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#define WM8766_FMT_MASK 0x003
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#define WM8766_FMT_RJUST 0x000
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#define WM8766_FMT_LJUST 0x001
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#define WM8766_FMT_I2S 0x002
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#define WM8766_FMT_DSP 0x003
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#define WM8766_LRP 0x004
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#define WM8766_BCP 0x008
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#define WM8766_IWL_MASK 0x030
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#define WM8766_IWL_16 0x000
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#define WM8766_IWL_20 0x010
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#define WM8766_IWL_24 0x020
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#define WM8766_IWL_32 0x030
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#define WM8766_PHASE_MASK 0x1c0
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/* DAC_CTRL2 */
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#define WM8766_ZCD 0x001
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#define WM8766_DZFM_MASK 0x006
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#define WM8766_DMUTE_MASK 0x038
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#define WM8766_DEEMP_MASK 0x1c0
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/* DAC_CTRL3 */
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#define WM8766_DACPD_MASK 0x00e
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#define WM8766_PWRDNALL 0x010
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#define WM8766_MS 0x020
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#define WM8766_RATE_MASK 0x1c0
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#define WM8766_RATE_128 0x000
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#define WM8766_RATE_192 0x040
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#define WM8766_RATE_256 0x080
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#define WM8766_RATE_384 0x0c0
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#define WM8766_RATE_512 0x100
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#define WM8766_RATE_768 0x140
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/* MUTE1 */
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#define WM8766_MPD1 0x040
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/* MUTE2 */
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#define WM8766_MPD2 0x020
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#endif
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