Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
35 lines
694 B
Plaintext
35 lines
694 B
Plaintext
C LB+fencembonceonce+ctrlonceonce
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(*
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* Result: Never
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*
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* This litmus test demonstrates that lightweight ordering suffices for
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* the load-buffering pattern, in other words, preventing all processes
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* reading from the preceding process's write. In this example, the
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* combination of a control dependency and a full memory barrier are enough
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* to do the trick. (But the full memory barrier could be replaced with
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* another control dependency and order would still be maintained.)
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*)
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{}
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P0(int *x, int *y)
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{
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int r0;
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r0 = READ_ONCE(*x);
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if (r0)
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WRITE_ONCE(*y, 1);
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}
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P1(int *x, int *y)
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{
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int r0;
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r0 = READ_ONCE(*y);
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smp_mb();
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WRITE_ONCE(*x, 1);
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}
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exists (0:r0=1 /\ 1:r0=1)
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