Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
92 lines
2.7 KiB
JSON
92 lines
2.7 KiB
JSON
[
|
|
{
|
|
"BriefDescription": "BACLEARS asserted.",
|
|
"Counter": "0,1",
|
|
"EventCode": "0xE6",
|
|
"EventName": "BACLEARS.ANY",
|
|
"SampleAfterValue": "2000000",
|
|
"UMask": "0x1"
|
|
},
|
|
{
|
|
"BriefDescription": "Cycles during which instruction fetches are stalled.",
|
|
"Counter": "0,1",
|
|
"EventCode": "0x86",
|
|
"EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED",
|
|
"SampleAfterValue": "2000000",
|
|
"UMask": "0x1"
|
|
},
|
|
{
|
|
"BriefDescription": "Decode stall due to IQ full",
|
|
"Counter": "0,1",
|
|
"EventCode": "0x87",
|
|
"EventName": "DECODE_STALL.IQ_FULL",
|
|
"SampleAfterValue": "2000000",
|
|
"UMask": "0x2"
|
|
},
|
|
{
|
|
"BriefDescription": "Decode stall due to PFB empty",
|
|
"Counter": "0,1",
|
|
"EventCode": "0x87",
|
|
"EventName": "DECODE_STALL.PFB_EMPTY",
|
|
"SampleAfterValue": "2000000",
|
|
"UMask": "0x1"
|
|
},
|
|
{
|
|
"BriefDescription": "Instruction fetches.",
|
|
"Counter": "0,1",
|
|
"EventCode": "0x80",
|
|
"EventName": "ICACHE.ACCESSES",
|
|
"SampleAfterValue": "200000",
|
|
"UMask": "0x3"
|
|
},
|
|
{
|
|
"BriefDescription": "Icache hit",
|
|
"Counter": "0,1",
|
|
"EventCode": "0x80",
|
|
"EventName": "ICACHE.HIT",
|
|
"SampleAfterValue": "200000",
|
|
"UMask": "0x1"
|
|
},
|
|
{
|
|
"BriefDescription": "Icache miss",
|
|
"Counter": "0,1",
|
|
"EventCode": "0x80",
|
|
"EventName": "ICACHE.MISSES",
|
|
"SampleAfterValue": "200000",
|
|
"UMask": "0x2"
|
|
},
|
|
{
|
|
"BriefDescription": "All Instructions decoded",
|
|
"Counter": "0,1",
|
|
"EventCode": "0xAA",
|
|
"EventName": "MACRO_INSTS.ALL_DECODED",
|
|
"SampleAfterValue": "2000000",
|
|
"UMask": "0x3"
|
|
},
|
|
{
|
|
"BriefDescription": "CISC macro instructions decoded",
|
|
"Counter": "0,1",
|
|
"EventCode": "0xAA",
|
|
"EventName": "MACRO_INSTS.CISC_DECODED",
|
|
"SampleAfterValue": "2000000",
|
|
"UMask": "0x2"
|
|
},
|
|
{
|
|
"BriefDescription": "Non-CISC macro instructions decoded",
|
|
"Counter": "0,1",
|
|
"EventCode": "0xAA",
|
|
"EventName": "MACRO_INSTS.NON_CISC_DECODED",
|
|
"SampleAfterValue": "2000000",
|
|
"UMask": "0x1"
|
|
},
|
|
{
|
|
"BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.",
|
|
"Counter": "0,1",
|
|
"CounterMask": "1",
|
|
"EventCode": "0xA9",
|
|
"EventName": "UOPS.MS_CYCLES",
|
|
"SampleAfterValue": "2000000",
|
|
"UMask": "0x1"
|
|
}
|
|
]
|