Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
57 lines
2.0 KiB
JSON
57 lines
2.0 KiB
JSON
[
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{
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"BriefDescription": "ASSISTS.PAGE_FAULT",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc1",
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"EventName": "ASSISTS.PAGE_FAULT",
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"SampleAfterValue": "1000003",
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"UMask": "0x8"
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},
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{
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"BriefDescription": "HW_INTERRUPTS.MASKED",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xcb",
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"EventName": "HW_INTERRUPTS.MASKED",
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"SampleAfterValue": "100003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "HW_INTERRUPTS.PENDING_AND_MASKED",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xcb",
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"EventName": "HW_INTERRUPTS.PENDING_AND_MASKED",
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"SampleAfterValue": "100003",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Number of hardware interrupts received by the processor.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xcb",
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"EventName": "HW_INTERRUPTS.RECEIVED",
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"PublicDescription": "Counts the number of hardware interruptions received by the processor.",
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"SampleAfterValue": "203",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts streaming stores that have any type of response.",
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"Counter": "0,1,2,3",
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"EventCode": "0x2A,0x2B",
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"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x10800",
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"PublicDescription": "Counts streaming stores that have any type of response. Available PDIST counters: 0",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Cycles the uncore cannot take further requests",
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"Counter": "0,1,2,3",
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"CounterMask": "1",
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"EventCode": "0x2d",
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"EventName": "XQ.FULL_CYCLES",
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"PublicDescription": "number of cycles when the thread is active and the uncore cannot take any further requests (for example prefetches, loads or stores initiated by the Core that miss the L2 cache).",
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"SampleAfterValue": "1000003",
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"UMask": "0x1"
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}
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]
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