Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
30 lines
1.8 KiB
JSON
30 lines
1.8 KiB
JSON
[
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{
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"BriefDescription": "Counts the number of floating operations retired that required microcode assists",
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"Counter": "0,1",
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"EventCode": "0xC3",
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"EventName": "MACHINE_CLEARS.FP_ASSIST",
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"PublicDescription": "This event counts the number of times that the pipeline stalled due to FP operations needing assists.",
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"SampleAfterValue": "200003",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Counts the number of packed SSE, AVX, AVX2, AVX-512 micro-ops (both floating point and integer) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies.",
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"Counter": "0,1",
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"EventCode": "0xC2",
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"EventName": "UOPS_RETIRED.PACKED_SIMD",
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"PublicDescription": "The length of the packed operation (128bits, 256bits or 512bits) is not taken into account when updating the counter; all count the same (+1). \r\nMask (k) registers are ignored. For example: a micro-op operating with a mask that only enables one element or even zero elements will still trigger this counter (+1)\r\nThis event is defined at the micro-op level and not instruction level. Most instructions are implemented with one micro-op but not all.",
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"SampleAfterValue": "200003",
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"UMask": "0x40"
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},
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{
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"BriefDescription": "Counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro ops), division, sqrt.",
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"Counter": "0,1",
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"EventCode": "0xC2",
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"EventName": "UOPS_RETIRED.SCALAR_SIMD",
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"PublicDescription": "This event is defined at the micro-op level and not instruction level. Most instructions are implemented with one micro-op but not all.",
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"SampleAfterValue": "200003",
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"UMask": "0x20"
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}
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]
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