Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
59 lines
2.1 KiB
JSON
59 lines
2.1 KiB
JSON
[
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{
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"BriefDescription": "Counts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front end.",
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"Counter": "0,1",
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"EventCode": "0xE6",
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"EventName": "BACLEARS.ALL",
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"SampleAfterValue": "200003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts the number of times the front end resteers for conditional branches as a result of another branch handling mechanism in the front end.",
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"Counter": "0,1",
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"EventCode": "0xE6",
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"EventName": "BACLEARS.COND",
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"SampleAfterValue": "200003",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "Counts the number of times the front end resteers for RET branches as a result of another branch handling mechanism in the front end.",
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"Counter": "0,1",
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"EventCode": "0xE6",
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"EventName": "BACLEARS.RETURN",
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"SampleAfterValue": "200003",
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"UMask": "0x8"
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},
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{
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"BriefDescription": "Counts all instruction fetches, including uncacheable fetches.",
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"Counter": "0,1",
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"EventCode": "0x80",
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"EventName": "ICACHE.ACCESSES",
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"SampleAfterValue": "200003",
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"UMask": "0x3"
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},
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{
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"BriefDescription": "Counts all instruction fetches that hit the instruction cache.",
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"Counter": "0,1",
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"EventCode": "0x80",
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"EventName": "ICACHE.HIT",
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"SampleAfterValue": "200003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding.",
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"Counter": "0,1",
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"EventCode": "0x80",
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"EventName": "ICACHE.MISSES",
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"SampleAfterValue": "200003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Counts the number of times the MSROM starts a flow of uops.",
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"Counter": "0,1",
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"EventCode": "0xE7",
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"EventName": "MS_DECODED.MS_ENTRY",
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"SampleAfterValue": "200003",
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"UMask": "0x1"
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}
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]
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