Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
45 lines
1.6 KiB
JSON
45 lines
1.6 KiB
JSON
[
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{
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"BriefDescription": "Unhalted core cycles when the thread is in ring 0.",
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"Counter": "0,1,2,3",
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"EventCode": "0x5C",
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"EventName": "CPL_CYCLES.RING0",
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"SampleAfterValue": "2000003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
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"Counter": "0,1,2,3",
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"CounterMask": "1",
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"EdgeDetect": "1",
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"EventCode": "0x5C",
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"EventName": "CPL_CYCLES.RING0_TRANS",
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"SampleAfterValue": "100007",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.",
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"Counter": "0,1,2,3",
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"EventCode": "0x5C",
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"EventName": "CPL_CYCLES.RING123",
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"SampleAfterValue": "2000003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .",
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"Counter": "0,1,2,3",
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"EventCode": "0x4E",
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"EventName": "HW_PRE_REQ.DL1_MISS",
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"SampleAfterValue": "2000003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.",
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"Counter": "0,1,2,3",
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"EventCode": "0x63",
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"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
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"SampleAfterValue": "2000003",
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"UMask": "0x1"
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}
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]
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