Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
89 lines
1.6 KiB
C
89 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include "../perf_regs.h"
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#include "../../../arch/riscv/include/uapi/asm/perf_regs.h"
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const char *__perf_reg_name_riscv(int id)
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{
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switch (id) {
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case PERF_REG_RISCV_PC:
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return "pc";
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case PERF_REG_RISCV_RA:
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return "ra";
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case PERF_REG_RISCV_SP:
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return "sp";
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case PERF_REG_RISCV_GP:
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return "gp";
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case PERF_REG_RISCV_TP:
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return "tp";
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case PERF_REG_RISCV_T0:
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return "t0";
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case PERF_REG_RISCV_T1:
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return "t1";
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case PERF_REG_RISCV_T2:
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return "t2";
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case PERF_REG_RISCV_S0:
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return "s0";
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case PERF_REG_RISCV_S1:
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return "s1";
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case PERF_REG_RISCV_A0:
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return "a0";
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case PERF_REG_RISCV_A1:
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return "a1";
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case PERF_REG_RISCV_A2:
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return "a2";
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case PERF_REG_RISCV_A3:
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return "a3";
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case PERF_REG_RISCV_A4:
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return "a4";
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case PERF_REG_RISCV_A5:
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return "a5";
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case PERF_REG_RISCV_A6:
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return "a6";
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case PERF_REG_RISCV_A7:
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return "a7";
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case PERF_REG_RISCV_S2:
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return "s2";
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case PERF_REG_RISCV_S3:
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return "s3";
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case PERF_REG_RISCV_S4:
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return "s4";
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case PERF_REG_RISCV_S5:
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return "s5";
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case PERF_REG_RISCV_S6:
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return "s6";
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case PERF_REG_RISCV_S7:
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return "s7";
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case PERF_REG_RISCV_S8:
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return "s8";
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case PERF_REG_RISCV_S9:
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return "s9";
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case PERF_REG_RISCV_S10:
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return "s10";
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case PERF_REG_RISCV_S11:
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return "s11";
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case PERF_REG_RISCV_T3:
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return "t3";
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case PERF_REG_RISCV_T4:
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return "t4";
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case PERF_REG_RISCV_T5:
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return "t5";
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case PERF_REG_RISCV_T6:
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return "t6";
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default:
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return NULL;
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}
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return NULL;
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}
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uint64_t __perf_reg_ip_riscv(void)
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{
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return PERF_REG_RISCV_PC;
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}
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uint64_t __perf_reg_sp_riscv(void)
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{
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return PERF_REG_RISCV_SP;
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}
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