Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
23 lines
816 B
Plaintext
23 lines
816 B
Plaintext
What: /sys/devices/platform/<platform>/etr3
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Date: Apr 2021
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KernelVersion: 5.13
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Contact: "Tomas Winkler" <tomas.winkler@intel.com>
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Description:
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The file exposes "Extended Test Mode Register 3" global
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reset bits. The bits are used during an Intel platform
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manufacturing process to indicate that consequent reset
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of the platform is a "global reset". This type of reset
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is required in order for manufacturing configurations
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to take effect.
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Display global reset setting bits for PMC.
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* bit 31 - global reset is locked
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* bit 20 - global reset is set
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Writing bit 20 value to the etr3 will induce
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a platform "global reset" upon consequent platform reset,
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in case the register is not locked.
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The "global reset bit" should be locked on a production
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system and the file is in read-only mode.
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