Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
71 lines
1.7 KiB
YAML
71 lines
1.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/perf/arm,smmu-v3-pmcg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Arm SMMUv3 Performance Monitor Counter Group
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maintainers:
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- Will Deacon <will@kernel.org>
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- Robin Murphy <robin.murphy@arm.com>
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description: |
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An SMMUv3 may have several Performance Monitor Counter Group (PMCG).
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They are standalone performance monitoring units that support both
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architected and IMPLEMENTATION DEFINED event counters.
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properties:
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$nodename:
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pattern: "^pmu@[0-9a-f]*"
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compatible:
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oneOf:
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- items:
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- const: arm,mmu-600-pmcg
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- const: arm,smmu-v3-pmcg
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- const: arm,smmu-v3-pmcg
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reg:
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items:
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- description: Register page 0
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- description: Register page 1, if SMMU_PMCG_CFGR.RELOC_CTRS = 1
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minItems: 1
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interrupts:
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maxItems: 1
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msi-parent: true
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required:
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- compatible
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- reg
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anyOf:
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- required:
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- interrupts
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- required:
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- msi-parent
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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pmu@2b420000 {
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compatible = "arm,smmu-v3-pmcg";
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reg = <0x2b420000 0x1000>,
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<0x2b430000 0x1000>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>;
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msi-parent = <&its 0xff0000>;
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};
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pmu@2b440000 {
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compatible = "arm,smmu-v3-pmcg";
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reg = <0x2b440000 0x1000>,
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<0x2b450000 0x1000>;
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interrupts = <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>;
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msi-parent = <&its 0xff0000>;
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};
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