Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
55 lines
1.0 KiB
Devicetree
55 lines
1.0 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree Include file for Marvell 98dx4521 family SoC
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*
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* Copyright (C) 2016 Allied Telesis Labs
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*
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* Contains definitions specific to the 98dx4521 SoC that are not
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* common to all Armada XP SoCs.
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*/
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#include "armada-xp-98dx3236.dtsi"
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/ {
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model = "Marvell 98DX4251 SoC";
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compatible = "marvell,armadaxp-98dx4251", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
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cpus {
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cpu@1 {
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device_type = "cpu";
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compatible = "marvell,sheeva-v7";
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reg = <1>;
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clocks = <&cpuclk 1>;
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clock-latency = <1000000>;
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};
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};
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soc {
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internal-regs {
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resume@20980 {
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compatible = "marvell,98dx3336-resume-ctrl";
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reg = <0x20980 0x10>;
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};
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};
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};
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};
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&sdio {
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status = "okay";
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};
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&pinctrl {
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compatible = "marvell,98dx4251-pinctrl";
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sdio_pins: sdio-pins {
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marvell,pins = "mpp5", "mpp6", "mpp7",
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"mpp8", "mpp9", "mpp10";
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marvell,function = "sd0";
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};
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};
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&pp0 {
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compatible = "marvell,prestera-98dx4251", "marvell,prestera";
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interrupts = <33>, <34>, <35>, <36>;
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};
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