Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
95 lines
2.0 KiB
Devicetree
95 lines
2.0 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree file for Marvell Armada AP807 Quad
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*
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* Copyright (C) 2019 Marvell Technology Group Ltd.
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*/
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#include "armada-ap807.dtsi"
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x000>;
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enable-method = "psci";
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#cooling-cells = <2>;
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clocks = <&cpu_clk 0>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&l2_0>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x001>;
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enable-method = "psci";
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#cooling-cells = <2>;
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clocks = <&cpu_clk 0>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&l2_0>;
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};
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cpu2: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x100>;
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enable-method = "psci";
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#cooling-cells = <2>;
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clocks = <&cpu_clk 1>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&l2_1>;
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};
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cpu3: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x101>;
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enable-method = "psci";
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#cooling-cells = <2>;
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clocks = <&cpu_clk 1>;
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&l2_1>;
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};
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l2_0: l2-cache0 {
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compatible = "cache";
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cache-size = <0x80000>;
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cache-line-size = <64>;
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cache-sets = <512>;
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cache-level = <2>;
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cache-unified;
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};
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l2_1: l2-cache1 {
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compatible = "cache";
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cache-size = <0x80000>;
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cache-line-size = <64>;
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cache-sets = <512>;
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cache-level = <2>;
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cache-unified;
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};
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};
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};
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