Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
70 lines
1.3 KiB
Devicetree
70 lines
1.3 KiB
Devicetree
/dts-v1/;
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/ {
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compatible = "opencores,or1ksim";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&pic>;
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aliases {
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uart0 = &serial0;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "uart0:115200";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x02000000>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "opencores,or1200-rtlsvn481";
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reg = <0>;
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clock-frequency = <20000000>;
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};
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cpu@1 {
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compatible = "opencores,or1200-rtlsvn481";
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reg = <1>;
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clock-frequency = <20000000>;
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};
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};
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ompic: ompic@98000000 {
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compatible = "openrisc,ompic";
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reg = <0x98000000 16>;
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interrupt-controller;
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#interrupt-cells = <0>;
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interrupts = <1>;
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};
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/*
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* OR1K PIC is built into CPU and accessed via special purpose
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* registers. It is not addressable and, hence, has no 'reg'
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* property.
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*/
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pic: pic {
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compatible = "opencores,or1k-pic-level";
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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serial0: serial@90000000 {
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compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
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reg = <0x90000000 0x100>;
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interrupts = <2>;
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clock-frequency = <20000000>;
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};
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enet0: ethoc@92000000 {
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compatible = "opencores,ethoc";
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reg = <0x92000000 0x800>;
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interrupts = <4>;
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big-endian;
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};
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};
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