Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
102 lines
2.7 KiB
C
102 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2013-2016 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*/
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#ifndef __MSM_FENCE_H__
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#define __MSM_FENCE_H__
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#include "msm_drv.h"
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/**
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* struct msm_fence_context - fence context for gpu
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*
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* Each ringbuffer has a single fence context, with the GPU writing an
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* incrementing fence seqno at the end of each submit
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*/
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struct msm_fence_context {
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/** @dev: the drm device */
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struct drm_device *dev;
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/** @name: human readable name for fence timeline */
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char name[32];
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/** @context: see dma_fence_context_alloc() */
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unsigned context;
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/** @index: similar to context, but local to msm_fence_context's */
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unsigned index;
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/**
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* @last_fence:
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* Last assigned fence, incremented each time a fence is created
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* on this fence context. If last_fence == completed_fence,
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* there is no remaining pending work
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*/
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uint32_t last_fence;
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/**
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* @completed_fence:
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* The last completed fence, updated from the CPU after interrupt
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* from GPU
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*/
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uint32_t completed_fence;
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/**
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* @fenceptr:
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* The address that the GPU directly writes with completed fence
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* seqno. This can be ahead of completed_fence. We can peek at
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* this to see if a fence has already signaled but the CPU hasn't
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* gotten around to handling the irq and updating completed_fence
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*/
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volatile uint32_t *fenceptr;
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/**
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* @spinlock: fence context spinlock
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*/
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spinlock_t spinlock;
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/*
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* TODO this doesn't really deal with multiple deadlines, like
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* if userspace got multiple frames ahead.. OTOH atomic updates
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* don't queue, so maybe that is ok
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*/
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/** @next_deadline: Time of next deadline */
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ktime_t next_deadline;
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/**
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* @next_deadline_fence:
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* Fence value for next pending deadline. The deadline timer is
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* canceled when this fence is signaled.
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*/
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uint32_t next_deadline_fence;
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/**
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* @deadline_timer: tracks nearest deadline of a fence timeline and
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* expires just before it.
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*/
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struct hrtimer deadline_timer;
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/**
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* @deadline_work: work to do after deadline_timer expires
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*/
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struct kthread_work deadline_work;
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};
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struct msm_fence_context * msm_fence_context_alloc(struct drm_device *dev,
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volatile uint32_t *fenceptr, const char *name);
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void msm_fence_context_free(struct msm_fence_context *fctx);
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bool msm_fence_completed(struct msm_fence_context *fctx, uint32_t fence);
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void msm_update_fence(struct msm_fence_context *fctx, uint32_t fence);
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struct dma_fence * msm_fence_alloc(void);
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void msm_fence_init(struct dma_fence *fence, struct msm_fence_context *fctx);
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static inline bool
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fence_before(uint32_t a, uint32_t b)
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{
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return (int32_t)(a - b) < 0;
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}
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static inline bool
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fence_after(uint32_t a, uint32_t b)
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{
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return (int32_t)(a - b) > 0;
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}
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#endif
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