Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
89 lines
2.0 KiB
C
89 lines
2.0 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#include <linux/math64.h>
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#include "xe_gt_clock.h"
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#include "regs/xe_gt_regs.h"
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#include "regs/xe_regs.h"
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#include "xe_assert.h"
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#include "xe_device.h"
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#include "xe_gt.h"
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#include "xe_gt_printk.h"
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#include "xe_macros.h"
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#include "xe_mmio.h"
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#define f19_2_mhz 19200000
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#define f24_mhz 24000000
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#define f25_mhz 25000000
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#define f38_4_mhz 38400000
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#define ts_base_83 83333
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#define ts_base_52 52083
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#define ts_base_80 80000
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static void read_crystal_clock(struct xe_gt *gt, u32 rpm_config_reg, u32 *freq,
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u32 *timestamp_base)
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{
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u32 crystal_clock = REG_FIELD_GET(RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK,
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rpm_config_reg);
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switch (crystal_clock) {
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case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
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*freq = f24_mhz;
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*timestamp_base = ts_base_83;
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return;
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case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
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*freq = f19_2_mhz;
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*timestamp_base = ts_base_52;
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return;
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case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ:
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*freq = f38_4_mhz;
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*timestamp_base = ts_base_52;
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return;
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case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ:
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*freq = f25_mhz;
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*timestamp_base = ts_base_80;
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return;
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default:
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xe_gt_warn(gt, "Invalid crystal clock frequency: %u", crystal_clock);
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*freq = 0;
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*timestamp_base = 0;
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return;
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}
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}
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int xe_gt_clock_init(struct xe_gt *gt)
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{
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u32 freq;
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u32 c0;
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c0 = xe_mmio_read32(>->mmio, RPM_CONFIG0);
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read_crystal_clock(gt, c0, &freq, >->info.timestamp_base);
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/*
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* Now figure out how the command stream's timestamp
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* register increments from this frequency (it might
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* increment only every few clock cycle).
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*/
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freq >>= 3 - REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, c0);
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gt->info.reference_clock = freq;
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return 0;
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}
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/**
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* xe_gt_clock_interval_to_ms - Convert sampled GT clock ticks to msec
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*
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* @gt: the &xe_gt
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* @count: count of GT clock ticks
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*
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* Returns: time in msec
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*/
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u64 xe_gt_clock_interval_to_ms(struct xe_gt *gt, u64 count)
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{
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return mul_u64_u32_div(count, MSEC_PER_SEC, gt->info.reference_clock);
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}
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