Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
100 lines
2.5 KiB
C
100 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* drxd_firm.h
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*
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* Copyright (C) 2006-2007 Micronas
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*/
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#ifndef _DRXD_FIRM_H_
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#define _DRXD_FIRM_H_
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#include <linux/types.h>
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#include "drxd_map_firm.h"
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#define VERSION_MAJOR 1
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#define VERSION_MINOR 4
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#define VERSION_PATCH 23
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#define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A
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#define DRXD_MAX_RETRIES (1000)
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#define HI_I2C_DELAY 84
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#define HI_I2C_BRIDGE_DELAY 750
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#define EQ_TD_TPS_PWR_UNKNOWN 0x00C0 /* Unknown configurations */
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#define EQ_TD_TPS_PWR_QPSK 0x016a
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#define EQ_TD_TPS_PWR_QAM16_ALPHAN 0x0195
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#define EQ_TD_TPS_PWR_QAM16_ALPHA1 0x0195
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#define EQ_TD_TPS_PWR_QAM16_ALPHA2 0x011E
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#define EQ_TD_TPS_PWR_QAM16_ALPHA4 0x01CE
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#define EQ_TD_TPS_PWR_QAM64_ALPHAN 0x019F
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#define EQ_TD_TPS_PWR_QAM64_ALPHA1 0x019F
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#define EQ_TD_TPS_PWR_QAM64_ALPHA2 0x00F8
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#define EQ_TD_TPS_PWR_QAM64_ALPHA4 0x014D
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#define DRXD_DEF_AG_PWD_CONSUMER 0x000E
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#define DRXD_DEF_AG_PWD_PRO 0x0000
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#define DRXD_DEF_AG_AGC_SIO 0x0000
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#define DRXD_FE_CTRL_MAX 1023
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#define DRXD_OSCDEV_DO_SCAN (16)
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#define DRXD_OSCDEV_DONT_SCAN (0)
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#define DRXD_OSCDEV_STEP (275)
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#define DRXD_SCAN_TIMEOUT (650)
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#define DRXD_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
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#define DRXD_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
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#define DRXD_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
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#define IRLEN_COARSE_8K (10)
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#define IRLEN_FINE_8K (10)
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#define IRLEN_COARSE_2K (7)
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#define IRLEN_FINE_2K (9)
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#define DIFF_INVALID (511)
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#define DIFF_TARGET (4)
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#define DIFF_MARGIN (1)
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extern u8 DRXD_InitAtomicRead[];
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extern u8 DRXD_HiI2cPatch_1[];
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extern u8 DRXD_HiI2cPatch_3[];
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extern u8 DRXD_InitSC[];
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extern u8 DRXD_ResetCEFR[];
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extern u8 DRXD_InitFEA2_1[];
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extern u8 DRXD_InitFEA2_2[];
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extern u8 DRXD_InitCPA2[];
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extern u8 DRXD_InitCEA2[];
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extern u8 DRXD_InitEQA2[];
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extern u8 DRXD_InitECA2[];
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extern u8 DRXD_ResetECA2[];
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extern u8 DRXD_ResetECRAM[];
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extern u8 DRXD_A2_microcode[];
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extern u32 DRXD_A2_microcode_length;
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extern u8 DRXD_InitFEB1_1[];
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extern u8 DRXD_InitFEB1_2[];
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extern u8 DRXD_InitCPB1[];
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extern u8 DRXD_InitCEB1[];
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extern u8 DRXD_InitEQB1[];
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extern u8 DRXD_InitECB1[];
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extern u8 DRXD_InitDiversityFront[];
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extern u8 DRXD_InitDiversityEnd[];
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extern u8 DRXD_DisableDiversity[];
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extern u8 DRXD_StartDiversityFront[];
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extern u8 DRXD_StartDiversityEnd[];
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extern u8 DRXD_DiversityDelay8MHZ[];
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extern u8 DRXD_DiversityDelay6MHZ[];
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extern u8 DRXD_B1_microcode[];
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extern u32 DRXD_B1_microcode_length;
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#endif
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