Greg Kroah-Hartman
598cf27219
Link: https://lore.kernel.org/r/20260217200002.683975158@linuxfoundation.org Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Takeshi Ogasawara <takeshi.ogasawara@futuring-girl.com> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Salvatore Bonaccorso <carnil@debian.org> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Mark Brown <broonie@kernel.org> Tested-by: Luna Jernberg <droidbittin@gmail.com> Tested-by: Ronald Warsow <rwarsow@gmx.de> Tested-by: Justin M. Forbes <jforbes@fedoraproject.org> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Miguel Ojeda <ojeda@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
94 lines
2.2 KiB
C
94 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* RZ/G3S System controller driver
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*
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* Copyright (C) 2024 Renesas Electronics Corp.
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*/
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#include <linux/bits.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include "rz-sysc.h"
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#define SYS_XSPI_MAP_STAADD_CS0 0x348
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#define SYS_XSPI_MAP_ENDADD_CS0 0x34c
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#define SYS_XSPI_MAP_STAADD_CS1 0x350
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#define SYS_XSPI_MAP_ENDADD_CS1 0x354
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#define SYS_GETH0_CFG 0x380
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#define SYS_GETH1_CFG 0x390
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#define SYS_PCIE_CFG 0x3a0
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#define SYS_PCIE_MON 0x3a4
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#define SYS_PCIE_ERR_MON 0x3ac
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#define SYS_PCIE_PHY 0x3b4
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#define SYS_I2C0_CFG 0x400
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#define SYS_I2C1_CFG 0x410
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#define SYS_I2C2_CFG 0x420
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#define SYS_I2C3_CFG 0x430
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#define SYS_I3C_CFG 0x440
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#define SYS_USB_PWRRDY 0xd70
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#define SYS_PCIE_RST_RSM_B 0xd74
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static const struct rz_sysc_soc_id_init_data rzg3s_sysc_soc_id_init_data __initconst = {
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.family = "RZ/G3S",
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.id = 0x85e0447,
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.devid_offset = 0xa04,
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.revision_mask = GENMASK(31, 28),
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.specific_id_mask = GENMASK(27, 0),
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};
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static bool rzg3s_regmap_readable_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case SYS_XSPI_MAP_STAADD_CS0:
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case SYS_XSPI_MAP_ENDADD_CS0:
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case SYS_XSPI_MAP_STAADD_CS1:
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case SYS_XSPI_MAP_ENDADD_CS1:
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case SYS_GETH0_CFG:
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case SYS_GETH1_CFG:
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case SYS_PCIE_CFG:
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case SYS_PCIE_MON:
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case SYS_PCIE_ERR_MON:
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case SYS_PCIE_PHY:
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case SYS_I2C0_CFG:
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case SYS_I2C1_CFG:
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case SYS_I2C2_CFG:
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case SYS_I2C3_CFG:
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case SYS_I3C_CFG:
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case SYS_USB_PWRRDY:
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case SYS_PCIE_RST_RSM_B:
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return true;
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default:
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return false;
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}
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}
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static bool rzg3s_regmap_writeable_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case SYS_XSPI_MAP_STAADD_CS0:
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case SYS_XSPI_MAP_ENDADD_CS0:
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case SYS_XSPI_MAP_STAADD_CS1:
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case SYS_XSPI_MAP_ENDADD_CS1:
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case SYS_PCIE_CFG:
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case SYS_PCIE_PHY:
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case SYS_I2C0_CFG:
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case SYS_I2C1_CFG:
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case SYS_I2C2_CFG:
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case SYS_I2C3_CFG:
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case SYS_I3C_CFG:
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case SYS_USB_PWRRDY:
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case SYS_PCIE_RST_RSM_B:
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return true;
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default:
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return false;
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}
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}
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const struct rz_sysc_init_data rzg3s_sysc_init_data __initconst = {
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.soc_id_init_data = &rzg3s_sysc_soc_id_init_data,
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.readable_reg = rzg3s_regmap_readable_reg,
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.writeable_reg = rzg3s_regmap_writeable_reg,
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.max_register = 0xe20,
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};
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